多晶矽奈米線元件特性與應用之研究

Abstract

在微電子技術發展過程，奈米線結構具有優越的電特性控制能力與較大的比表面積, 因此被視為奈米電子與感測元件的最佳選擇。在此論文中，我們以多晶矽奈米線薄膜電晶體為基礎，提出不同元件結構以期增進非揮發性記憶體與無接面電晶體之電特性。除此之外，我們也利用這種簡單且低成本的側壁間隙技術(sidewall spacer formation technology)，開發高靈敏度之多晶矽奈米線生醫感測器。 首先，我們藉由側壁間隙所形成之尖端角隅，應用於電場增強式SONOS (silicon-oxide-nitride-oxide-silicon)記憶體，並探討全包覆式閘極(gate-all-around)、Ω型閘極、魚鰭型與斜邊型等不同元件結構對於SONOS記憶體之影響。由於全包覆式閘極結構擁有較佳之閘極控制能力，因而可展現出較高的開關電流比與較陡峭的次臨界擺幅。經由元件模擬，我們發現利用角隅之尖端幾何結構能有效提升通道與二氧化矽穿隧層介面之電場值( ~ 40 MV/cm)，反觀斜邊型之電場值只有8.5 MV/cm，兩者相差近4.7倍之多。藉由此電場增強的設計方案，全包覆式閘極結構因具備三個角隅，故能有效提升SONOS記憶體之寫入/抹除速度與提供較大的記憶體視窗。另外，實驗結果顯示此尖端效應對於記憶體在初始1µs寫入時間的影響最大，其中又以全包覆式閘極結構最為明顯。這是因為SONOS記憶體在大電場的操作下，能將通道中的電子於相當短的操作時間注入氮化矽儲存層所致。然而，採用此電場增強方式所製備之記憶體元件，其二氧化矽穿隧層會因大電場而遭遇到嚴厲的破壞，導致忍耐力(endurance)與10年電荷保持能力(retention)均易產生劣化。 為了進一步增加記憶體元件之穿隧層電場，我們利用二氧化鉿與氧化鋁等高介電常數材料來取代傳統SONOS 元件之二氧化矽阻擋層。雖然提高阻擋層之介電常數能有效增進記憶體元件之寫入/抹除效率，然而其大電場對於二氧化矽穿隧層的傷害依然會使記憶體元件有較差的可靠性。因此，為了改善上述的缺點，我們藉由介電層工程提出了兩種新穎電荷儲存式記憶體，分別為TiN/alumina/nitride/vacuum/silicon (TANVAS) 與 TiN/hafnia/nitride/vacuum/silicon (THNVAS) 元件。藉由真空穿隧層空無一物的特性，可降低大電場對於穿隧層造成的破壞而大幅提升記憶體之耐久度。而採用TANVAS 與 THNVAS結構亦能有效增加電荷保存能力，其歸因於真空可抑制穿隧層之缺陷輔助穿隧 (trap-assist-tunneling)效應。此外，將穿隧氧化層置換成真空並搭配高介電常數阻擋層的使用能進一步提升穿隧層電場，同時降低阻擋層電場。實驗結果發現，由於THNVAS具備較高的阻擋層/穿隧層介電常數比值，因此該元件擁有最快速的寫入/抹除速度，在閘極電壓為+12/-12 V的操作條件下可以於10毫秒內分別得到3.75 V和4.97 V臨界電壓的改變，相信對於未來系統面板與高速快閃記憶體的開發有相當大的助益。 在無接面薄膜電晶體的研究中，我們探討了不同通道厚度對於元件電特性的影響。經由微縮通道厚度的方式，可將無接面薄膜電晶體之臨界電壓調整至理想值，且無需使用複雜的互補式複晶矽閘極與金屬閘極製程。其結果顯示，當奈米線厚度微縮至7.9奈米時，無接面薄膜電晶體擁有優越的電特性，包含合理的臨界電壓(Vth = 0.2 V)，較大的開關電流比(1.33×108)，極陡峭的次臨界擺幅(85 mV/dec)與較低的DIBL值(0.024 V/V)。此外，與傳統反轉式電晶體相較，無接面薄膜電晶體可展現出較大的轉導與導通電流，其中的原因與兩者之傳導機制與串聯阻值有關。在電特性可靠度方面，無接面薄膜電晶體具有較佳的定閘極電壓與定汲極電流可靠度表現，主要歸因於該元件可降低通道中的電場，此與我們模擬的結果相吻合。本論文也針對無接面薄膜電晶體進行低頻雜訊分析，由於該元件導通時的主要傳導路徑是位於奈米線的中心，因此較不易受到二氧化矽/多晶矽介面的干擾，故相較於傳統反轉式電晶體，無接面薄膜電晶體之低頻雜訊可大幅下降約100倍之多。另外，我們進一步將無接面薄膜電晶體的概念應用於SONOS記憶體並驗證其可行性，發現以此方法所製作的記憶體擁有較快的寫入速度與較佳的電荷保持能力。 本論文的最後利用這種簡單且低成本的側壁間隙技術，將多晶矽奈米線結合高介電常數之介電層開發高靈敏度酸鹼感測器。為了避免傳統感測元件浸泡在水溶液中而易在源極與汲極之間產生漏電流等問題，我們運用一種具有毛細力原子力顯微鏡探針之滴定技術。首先，利用聚焦離子束(focus-ion-beam)蝕刻原子力顯微鏡探針並在其針尖產生一小凹槽，藉由毛細力將待測溶液鎖在探針的凹槽內並準確塗佈於感測元件的表面。此方法可將待測物覆蓋於感測元件之介電層，並在乾式的環境下進行酸鹼值感測，搭配多晶矽奈米線具有較大比表面積的特性，我們只需要相當微量之pH 緩衝液即可偵測其酸鹼值。本論文亦探討了不同介電層材料對於感測元件的影響，實驗結果顯示，與傳統二氧化矽薄膜相較，採用高介電常數之介電層可展現較靈敏的酸鹼離子感測度，其中又以二氧化鉿薄膜表現最佳(138.7 nA/pH)，歸因於二氧化鉿具有高於氧化鋁薄膜之介電常數及擁有高於二氧化鈦薄膜之能隙。此技術之開發將有助於微量生醫感測的應用。 在本論文中，我們提出了簡單且便宜的方式來製作電場增強式記憶體、高性能之無接面電晶體與高靈敏度之多晶矽奈米線感測器，此技術之開發非常適合於未來系統面板、三維積體電路與生醫感測晶片整合的應用。

Nanowire structure has been considered as the best option for keeping the scaling trends of the microelectronics technology owing to the superior electrical controllability and large surface-to-volume ratio. In this thesis, various device structures based on nanowire poly-Si thin film transistors (TFTs) configuration were proposed to improve the performance of nonvolatile memory devices and junctionless (JL) transistors. In addition, the poly-Si nanowires fabricated via a simple and low cost sidewall spacer formation technology also demonstrate the highly potential for the ultrasensitive biochemical sensor application. At first, the field-enhanced poly-Si TFT silicon–oxide–nitride–oxide–silicon (SONOS) with various architectures including gate-all-around (GAA), omega-gate, FinFET, and bevel devices are studied in details. Owing to the superior gate control ability, the poly-Si TFT SONOS with GAA structure exhibits higher on/off ratio and stepper subthreshold swing (SS).The simulation results show that the local electric field at channel/tunneling oxide interface (to be ~ 40 MV/cm) can be effectively promoted by virtue of sharp corner geometry, which is about 4.7 times higher than the bevel structure (to be ~ 8.5 MV/cm). Based on such field enhanced scheme, the GAA structure with three sharp corners exhibits the faster P/E speed and larger memory window. It is found that sharp corner has a most profound influence on the preliminary program time of 1 µs, especially visible in GAA structure since the field-enhanced carriers can be injected into the nitride layer within a very short operation time. However, as observed experimentally, the Vth increment during P/E cycling stress and data loss after 10 years retention time are more severe in GAA structure due to the serious tunneling oxide damage from high electric field. For further increasing the local electric field at tunneling layer, the hafnia and alumina high-κ blocking oxide layers are adopted to replace the conventional TEOS blocking oxide. Although the P/E speed can be increased with the dielectric constant of blocking layer, the endurance and data retention are also significantly degraded via such a field-enhanced structure. In order to immunize these effects, two kinds of dielectric-engineered trapping charge poly-Si TFT memories with TiN/alumina/nitride/vacuum/silicon (TANVAS) and TiN/hafnia/nitride/vacuum/silicon (THNVAS) structures have been demonstrated with excellent P/E efficiency and much-improved reliability as well. The empty feature of vacuum would ensure the memory device free of defect creation within the tunneling layer, leading to the superior endurance characteristics for the THNVAS and TANVAS devices. The poly-Si TFT memory with vacuum tunneling layer also presents better charge-retention characteristics due to the suppression of trap-assist-tunneling effect in tunneling layer. In addition, introduction of the vacuum tunneling layer and high-k blocking layer can further promote the electric-field across the tunneling layer and simultaneously reduce the electric field of blocking layer. The experimental results show that the THNVAS device exhibits the largest Vth shifts of 3.75 and 4.97 V at VGS = +12/-12 V in 10 ms, accordingly. The outstanding features of this structure lie in the concept of the enlarged k-ratio of blocking/tunneling layers. Such excellent characteristics of poly-Si TFT memory with TiN/high-κ/nitride/vacuum/silicon structure will be an attractive device for future system-on-panel (SOP) and high-speed flash applications. In the study of JL transistors, the n-type GAA JL poly-Si TFTs in conjunction with n+ poly-gate with various channel thicknesses are systematically investigated. By reducing the channel thickness, the Vth of JL poly-Si TFT can be adjusted to an adequate value without the complicate counter-doped poly-gate or metal gate process. Experimental results reveal that the JL device with a channel thickness of 7.9 nm shows excellent electrical performance including desirable Vth of 0.2 V, excellent electrostatic control with high on/off ratio (1.33×108), small subthreshold slope (SS = 85 mV/dec), and ultralow DIBL value (0.024 V/V). As compared with conventional inversion-mode (IM) device, the JL device exhibits the similar switch behavior to the IM device for the smallest channel thickness of 7.9 nm. Furthermore, the JL devices also present superior gm value and on current, attributed to the bulk conduction mechanism as well as reduced series resistance in JL devices. Another advantage of JL devices is that the electrical reliability such as constant gate voltage stress and constant drain current stress can be greatly improved, even for the very small channel thickness devices. The JL transistor demonstrates less reliability degradation owing to the reduced electric field in the channel region, which is in agreement with the simulated results. Low frequency noise (LFN) analysis for both devices are also presented in this work, the bulk conduction phenomenon of JL device gives rise to a smaller value of LFN with respect to the IM counterpart by more than two orders. In addition, the combination of JL poly-Si TFT with SONOS memory has been demonstrated with superior program speed and much improved retention characteristics. Finally, the dry-type poly-Si nanowire pH-sensors coated with high-k dielectrics have been also demonstrated with the aid of novel focus-ion-beam (FIB) engineered capillary atomic-force-microscopy (C-AFM) tip. By means of this C-AFM tip coating technique, the relatively few testing solution can be transferred onto the surface of nanowire, preventing the sensor device from the immersion in the liquid and therefore suppressing the possible leakage current from the testing solution. As compared with the TEOS SiO2, the pH-sensors composed of Al2O3, TiO2, and HfO2 high-k materials exhibit the better sensitivities due to their enhanced capacitances. The best sensitivity (138.7 nA/pH) for HfO2 dielectric can be ascribed to the higher k-value and larger band gap with respect to the Al2O3 and TiO2, accordingly. Consequently, the C-AFM tip coating technique incorporating with HfO2 dielectric suggests the potential for the detection of minute quantity of biomedicines. In this thesis, a simple and costless process have been proposed to construct the field-enhanced nonvolatile memory, high performance JL transistor and high sensitivity poly-Si nanowire sensor, which presents a great potential in the application of SOP, 3-D integrated circuits and biochemical sensors.