标题: 生医应用系统单晶片之FPGA 实现
FPGA Implementation of Biomedical Application SoC
作者: 杨寓钧
Yang, Yu-Chun
林进灯
Lin, Chin-Teng
电控工程研究所
关键字: Radix-22 FFT;定点数;ICA;生医讯号;SDRAM控制器;VGA控制器;Radix-22 FFT;fixed-point;ICA;biomedical signal;SDRAM controller;VGA controller
公开日期: 2008
摘要: 在目前生医电子领域研究中,如何能够即时处理与分析大量的生理讯号是一个重要的讨论问题。以往电子医疗和分析仪器都相当庞大且价格贵,因此可携式与嵌入式的生医电子产品,需求日益增加。基于这两个原因,本论文提出生医应用系统单晶片的设计,以提供资源整合性的使用。

本论文提出一个生医讯号处理的系统单晶片设计,具有(1)可程式化的监控与分析生理讯号能力及(2)整合性硬体扩充的空间:只要配置好暂存器存取位址,便能将客制化硬体设计透过系统汇流排整合进系统中。此系统单晶片架构包含可程式化的中央处理器、生医讯号处理单元、系统汇流排、通讯和显示介面。可程式化的中央处理器负责系统程序的排程和输出入控制;生医讯号处理单元能对生理讯号做讯号分离与分析的数位讯号处理核心;系统汇流排的设计能够方便数位讯号处理IP 的加入与移除。

经由实验的结果显示,本论文所提出生医系统单晶片架构能在FPGA 的平台上以100 MHz 执行频率达到讯号即时分析与显示解析波形的效果。因为透过硬体执行与其他高速DSP 的使用有很大的节省空间,如较少执行的周期、较低的功率消耗、减少PCB 设计的面积等。最后,本论文所提出的架构透过FPGA 实现并在Altera DE2 发展板展示,共使用29,640 逻辑单元。
In the study of biomedical electronics nowadays, processing and analyzing masses of physiological signals in time is a critical issue in real world. In the past, electronic treatment and analysis instruments are very expansive and large. Therefore, the requirement of portable and embedded biomedical electronic product is growing rapidly. Based on these two reasons, this thesis presents a system-on-chip (SoC) design for biomedical applications to provide the integration of systematic resources.

In this thesis, the SOC design for biomedical signal processing is presented. It has the following features. (1) The ability of programmable monitoring and analyzing biomedical signals. (2) The flexibility for further hardware extension. The SoC design is composed of a programmable CPU, biomedical signal processing (BSP) units, system bus, communication, and display interface. The programmable CPU manages the process schedule and I/O control. The BSP unit is treated as digital signal processing (DSP) cores which can separate and analyze physiological signals. The system bus makes it flexible to add or to remove DSP IPs.

By experimental results, the proposed design implemented on FPGA can achieve real-time analysis and waveform displays under at 100 MHz. Comparison with other high-speed DSP processors, the system presents some optimization such as less execution cycles, lower power consumption, use of fewer PCB area. Finally, the SoC design is demonstrated in this thesis with the Altera DE2 development board. The whole design is consisted of 29,640 logic elements.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079512538
http://hdl.handle.net/11536/41087
显示于类别:Thesis


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