深次微米低壓次能帶隙電壓參考源電路設計

Abstract

此論文提出一個能操作在1-V電源電壓下之次能帶隙電壓參考源. 且其參考電壓輸出亦為低於1-V之電路架構. 所完成的晶片是一個適用於電池供電的系統整合晶片之應用。目的是能夠實現一個簡單，穩定，低成本，低電壓，低功率消耗的參考電壓源而能夠很容易的使用在可攜式裝備上。 這個晶片的製作是以台灣積體電路製造股份有限公司提供的90nm 低功率互補式金氧半導體製程技術實現。整個晶片設計包含一個低壓運算放大器，電流鏡，及一個次能帶隙電壓產生器核心電路。 量測結果顯示，次能帶隙電壓參考源可以操作在 1-V電源電壓。 但其輸出參考電壓會隨電壓源而變動。為改善此特性，重新設計了低壓運算放大器，電流鏡，低電壓啟動器,及加入一個直流偏壓源。模擬結果顯示輸出參考電壓不再會隨電壓源而變動，且其工作電壓能低至0.8伏特並具有溫度係數60ppm/□C。在1-V電源電壓下有44□W的功率消耗

This thesis proposed a design of 1-V sub-bandgap voltage reference generator circuit. It is suitable for battery-based System-On-Chip applications. The goal of this design is to realize a simple, low cost, low voltage, and low power consumption sub-bandgap voltage reference generator and it can be easy to use for portable equipments. This chip was fabricated using TSMC 90nm CMOS logic process technology provided by Taiwan semiconductor manufacturing company. Whole chip includes a low voltage operational amplifier, current source, and a sub-bandgap core voltage generator circuit. The measured results show that the sub-bandgap voltage reference generator can be operated at 1-V power supply, but the output reference voltage will vary with power supply. To improve the circuit performance, the low voltage operational amplifier, the current mirror and low voltage start up circuit are re-designed, in additional with a DC bias circuit. The simulation result shows the VDDmin can achieve 0.8V with 60ppm/□C in new circuit. The power dissipation is 44□W with 1-V power supply.