多閘極多通道電晶體特性擾動暨 奈米裂縫場發射特性之研究

Abstract

金氧半場效應電晶體通道長度微縮至32奈米之後，仍保有高性能之立體矽場效電晶體，因而備受學/業界注目，但唯有完整了解其元件特性才能助於延續摩爾定律。本研究探討閘極具不同長寬比(aspect ratio/AR)之16奈米三通道立體矽場效電晶體的電特性，就元件特性而言，發現單通道之鰭式場效電晶體(AR = 2)，比起具單通道之三閘極場效電晶體(AR = 1)與類平面場效電晶體(AR = 0.5)，有較佳之通道控制，而三通道場效電晶體之電特性又比單通道場效電晶體好。進而探討單通道與三通道電晶體組成的6T靜態隨機存取記憶體(SRAM)電路特性，以及反相器電路的暫態特性，研究發現多通道的缺點在於大電容，電路上的設計需格外小心。就擾動分析而言，隨機摻雜造成的表面電位擾動，在鰭式場效電晶體結構，比起三閘極與類平面場效電晶體結構，仍然較均勻，不僅成功壓抑元件特性擾動，也成功壓抑電路特性擾動。此論文結果對於三通道場效電晶體之DC與電路特性之推估以及下世代電晶體擾動特性分析極有助益。 由於影像顯示產業是兩兆雙星產業發展計畫的其中之一，可見此產業的重要性，因此，本研究將繼續探討在表面傳導電子發射元件(Surface Conduction Electron-Emitter Display, SED) 用於顯示科技技術之工作，我們利用其簡單結構與實驗數據校正後所得之參數，帶入三維有限差分時域粒子式的電磁模擬方法中，成功模擬利用高壓氫製作出奈米級鈀金屬裂縫做為表面傳導電子發射的發射源之電子傳導特性與發射效率。利用此數值計算技術，目前已知使用高壓氫處理，比用聚焦離子束系統製作出的奈米級鈀金屬裂縫，擁有較好的場發射效率，我們將進一步地探討奈米級鈀金屬裂縫，在不同寬度、厚度與傾斜角度變化下，對場發射的影響，並試著在合理結構設定範圍內，找到擁有最佳發射效率之幾何結構設定。在模擬過程中，除了比較不同幾何結構下之場發射特性外，同時也說明其傳導機制、發射效率及在陽極版的電流密度分佈，此研究對新世代平面顯示器技術的突破，有很大的幫助。 總之，本論文以實驗驗證過的模擬技術完成奈米元件與奈米裂縫的研究。論文的第一部份已經模擬分析了多通道多重閘極場效應電晶體元件與電路遭受隨機摻雜擾動影響下的DC、AC、以及動態操作特性。論文的第二部份模擬、分析與設計了奈米級鈀金屬裂縫，在不同幾何結構與參數變化下，奈米裂縫對場發射的影響，並找尋最佳發射效率之幾何結構設定。

As the gate length of a metal oxide semiconductor field effect transistor (MOSFET) decreases below 32 nm, vertical channel transistors have attracted much attention because of their many interesting characteristics. Full realization of their characteristics benefits us to continue Moore's Law. Therefore, this study explores the electrical characteristics of 16 nm triple-fin FinFETs with different fin aspect ratios [AR = fin height (Hfin) / fin width (Wfin)]. For device characteristics, the single-fin FinFET (AR = 2) has better channel controllability than the single-fin tri-gate (AR = 1) and single-fin quasi-planar (AR = 0.5) FETs. The performance is improved, as the number of fin increases. Further, the electrical characteristics of six-transistor (6T) static random access memory (SRAM) and transient characteristics of inverter using single-/triple-fin FETs are investigated, respectively. We find that the multi-fin FET has larger capacitance and its circuit implementation should be carefully designed. For fluctuation analysis, the random-dopant-induced surface potential fluctuation in FinFETs is more uniform than that of tri-gate and quasi-planar FETs. The FinFET suppresses not only the fluctuation at the device level, but also at the circuit level. The results of this study provide insight into the DC and circuit characteristics of FinFET structure and benefit the fluctuation analysis for next-generation transistors. As we know, the flat panel display (FPD) is one of promoting policy of "Two Trillion and Twin Star" which plays an important role in Economy of Taiwan. Therefore, based on the previous study of display technology, we keep exploring the field emission of surface conduction electron-emitter display (SED). We get the parameters from the calibration between 3D simulation and measurement data. Then the parameters are input into 3-D finite-difference time-domain particle-in-cell (FDTD-PIC) model to simulate the electron conducting mechanism and emission efficiency of nanoscale Pd think-film strip by hydrogen absorption regarded as the source of surface conduction electron-emitters. Using this model, we find that the field emission of palladium (Pd) thin-film strips by hydrogen absorption has better field emission compared with made by focus ion beam technique. We further explore the effect of field emission under different tilted angle, separation width and thickness of Pd. Within the certain geometry setting, we have first found the optimal configuration of SCEs for better field emission. During the simulation work, the comparisons of field emission, current distribution on anode with different geometry are presented. This study benefits the innovation for new generation flat panel display technology. In summary, the studies of nanodevice and nanogap have been completed by using an experimentally validated simulation program. In the first part, I have already investigated the DC/AC and dynamic characteristic fluctuation induced by random dopant in multi-fin multi-gate MOSFET device and circuit, respectively. In the second part, I have performed the field emission simulation, analysis and design optimization of Pd thin-film strips under different geometry and parameters.