| 標題: | ON THE DESIGN OF VLSI ARCHITECTURES FOR PARALLEL EXECUTION OF DO LOOPS |
| 作者: | CHEN, Z CHANG, CC CHIA, TL 資訊科學與工程研究所 Institute of Computer Science and Engineering |
| 公開日期: | 1-四月-1990 |
| URI: | http://hdl.handle.net/11536/4132 |
| ISSN: | 0743-7315 |
| 期刊: | JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING |
| Volume: | 8 |
| Issue: | 4 |
| 起始頁: | 393 |
| 結束頁: | 399 |
| 顯示於類別： | 期刊論文 |
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- A two-level scheduling method: an effective parallelizing technique for uniform nested loops on a DSP multiprocessor / Lee, YH;Chen, C
- An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters / Wu, BF;Hu, YQ
- 迴圈多疊代之資料流執行 / 劉嘉修;Jie-Shiou Liu;單智君;Jean Jyh-Jiun Shann
- Parallel distance transforms on a linear array architecture / Chia, TL;Wang, KB;Chen, Z;Lou, DC
- PPD: A practical parallel loop detector for parallelizing compilers on multiprocessor systems / Yang, CT;Wu, CT;Tseng, SS
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