高解析度新測試技術之脈波寬度調變週期量測

Abstract

本論文提出一個高解析度的新測試技術，利用ATE (Automated Test Equipment)的數位量測通道在系統晶片上達成脈波寬度調變週期量測，且僅需要雙比較器即可完成此一測試方法。它可改善傳統測試方式,不受限於測試機台的取樣率,我們從研究理論的觀點來探討此新的量測方式並且減少測試成本、降低測試時間及增加產出率。 本文實現了一個增加PWM量測解析度的方法，利用coherent取樣定理我們可以達到小於1%解析度的誤差值，並且在SOC晶片裡只需用FT1(Final Test One)，它節省了FT2(Final Test Two)所造成的額外量產成本約17%。

This thesis proposes a novel and high resolution measurement technique on SOC for PWM Ton、Toff and Duty testing by use of logic test channel of an ATE. It accomplishes Duty cycles measurement by use of dual comparators only. We would like to investigate a novel approach to reduce the test cost and raising the through put as well as reduce the test time from a theoretical point of view. The key idea is to use the 1-bit digitizer of a digital test channel. Coherent sampling is to extend the capabilities of test equipment with a limited sampling frequency for the analysis of high-resolution signals. This thesis achieves the goal for improving the resolution with coherent sampling theorem. The method is able to achieve less than 1% error resolution. It can save testing costs at lest 17% in the SOC chip testing.