| 標題: | THE SIGNAL DELAY IN INTERCONNECTION LINES CONSIDERING THE EFFECTS OF SMALL-GEOMETRY CMOS INVERTERS |
| 作者: | SHIAU, MC WU, CY 電控工程研究所 Institute of Electrical and Control Engineering |
| 公開日期: | 1-Mar-1990 |
| URI: | http://dx.doi.org/10.1109/31.52736 http://hdl.handle.net/11536/4159 |
| ISSN: | 0098-4094 |
| DOI: | 10.1109/31.52736 |
| 期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS |
| Volume: | 37 |
| Issue: | 3 |
| 起始頁: | 420 |
| 結束頁: | 425 |
| Appears in Collections: | Articles |
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- DELAY MODELS AND SPEED IMPROVEMENT TECHNIQUES FOR RC TREE INTERCONNECTIONS AMONG SMALL-GEOMETRY CMOS INVERTERS / WU, CY;SHIAU, MC
- A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus / Li, Katherine Shu-Min;Lee, Chung-Len;Su, Chauchin;Chen, Jwu E.
- Interconnect accelerating techniques for sub-100-nm gigascale systems / Huang, HY;Chen, SL
- Modeling of interconnect capacitance, delay, and crosstalk in VLSI / Wong, SC;Lee, GY;Ma, DJ
- EFFICIENT PHYSICAL TIMING MODELS FOR CMOS AND-OR-INVERTER AND OR-AND-INVERTER GATES AND THEIR APPLICATIONS / WU, CY;SHIAU, MC
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