射頻金氧半場效電晶體元件佈局對高頻特性與低頻雜訊之影響以應用於射頻與類比電路

Abstract

本論文主要是探討元件佈局造成的STI應力，和經由STI製程頂邊所產生的圓角TCR (Top Corner Rounding)與隨之而來的dW效應對直流I-V特性、電導(Gm)，以及載子遷移率(ueff)的影響。同時我們也分析此兩種機制對元件低頻雜訊與高頻特性所產生的影響。為了提高的STI垂直方向的應力，我們設計了狹窄型OD和多重OD MOSFETs兩種元件，其概念是由標準多指元件(Standard multi-finger MOSFETs)延伸而來的。而維繞式MOSFET是我們所設計的另一種全新結構，它在從垂直方向完全不受到STI應力影響，關鍵就是在於它完全在width方向避開了的STI/OD界面，並藉此改善低頻雜訊。 但是在某些元件的量測結果顯示，我們無法從STI的應力解釋在極端狹窄的元件的反而有更低的低頻雜訊。因次我們從STI頂邊TCR導致的dW的角度去分析，推導出一semi-empirical模型，能夠模擬以預測width微縮對ueff 與Gm之影響，藉由這些模型可以準確的求出有效的通道寬度Weff。 STI應力愈強將導致介面缺陷電荷(Nit)的增加，但是此效應確遠不及dW明顯，對於狹窄型元件來說是一項優點。但不幸的是狹窄型元件的截止頻率還是會因為Cgg 增加而下降，而且無法經由去寄生的方式改善。 在低頻雜訊與高頻特性之間有著權衡的RF元件佈局設計考量。因此基板接點的元件設計是一個有趣的課題，我們設計各種基板接點結構的4-port 測試元件並將基板端獨立接出來，將我們提出新的body network模型萃取元件參數如基板電阻，它影響高頻元件特性與低頻雜訊特性。量測結果顯示愈大的基板電阻會產生愈大的低頻雜訊，我們可以藉由多重環狀佈局的方式設計基板接點形狀，藉此大量降低基板電阻，但同樣地此舉也會使閘極至基板接點間的雜散電容增加而降低截止頻率。

The impact of layout dependent STI stress and dW from STI top corner rounding (TCR) on I-V characteristics, transconductance (Gm), effective mobility (ueff), low frequency noise (LFN), and high frequency performance has been investigated in this thesis. Narrow-OD and multi-OD MOSFETs are two structures derived from standard multi-finger MOSFET for enhancing transverse stress. Donut MOSFET is another structure created to keep free from transverse stress, due to the elimination of STI/OD boundary along the channel width direction. The compressive stress from STI cannot explain the lower LFN in extremely narrow devices. STI top TCR induced dW is identified as an important factor responsible for the increase of Gm and the reduction of LFN with width scaling to nanoscale regime. A semi-empirical model was derived to simulate □eff degradation from STI stress and the increase of effective width (Weff) from dW. The proposed model can accurately predict width scaling effect on Gm based on a trade-off between □eff and Weff. The enhanced STI stress may lead to an increase of interface traps density (Nit) but the influence is relatively minor and overcome by Weff effect. Unfortunately, the extremely narrow devices suffer fT degradation due to an increase of Cgg, which cannot be eliminated even through an improved open deembedding. The trade-off between LFN and high frequency performance provides an important layout guideline for analog and RF circuit design. Body contact layout effect on LFN and high frequency performance is one more interesting topic of research in this thesis. Four-port test structures were implemented to accommodate 4-terminal MOSFETs with separate body terminal and a new body network model has been developed to simulate the body contact layout and body biases effects. The measurement result reveals that the higher body resistance will lead to the worse LFN characteristic. We can significantly reduce the body resistance by applying multi-ring body contacts, but this may contribute larger parasitic capacitance from poly gate to body contacts and hence lead to lower fT.