基板雜訊隔離結構設計與分析以應用於射頻與類比電路

Abstract

在本論文中，我們由頻域的觀點來探討射頻積體電路或高頻元件的應用，與其在基板雜訊的影響下之效應與缺點，引入各種文獻所闡釋的論點，整理出對於提升基板雜訊隔離度的各種結構、方法與優缺點；並且設計研製兩種基板雜訊隔離結構以進行量測分析與理論驗證。 第一部份的設計包括N型與P型之雜訊入侵源(aggressor)和雜訊受侵者(victim)搭配不同的保護環共有四種結構，目的是為了觀察訊號端和基板之間有了保護環的隔離是否有助於提升基板雜訊隔離度；另外再搭配不同結構的保護帶，而這些保護帶的結構也大致與保護環是類似的，其目的是為了在雜訊入侵源和受侵者之間有一道屏障以擋住基板雜訊的流通。而在直觀上，雜訊入侵源和受侵者的間距對於基板雜訊隔離度也是一個很重要的參數，所以亦設計不同間距搭配各種結構來觀察間距對於提升基板雜訊隔離度的關係。 第二個部份的設計中，雜訊入侵源和受侵者均為P型，即P+擴散區於P型基板，因此，入侵源只有一種保護環的結構，就是利用N-Well 和deep N-Well將之包圍住，而接受端有兩種保護環的結構，第一種跟入侵源的保護環結構是一樣的，有deep N-Well；另外一種是P型外圍只有N-Well而無deep N-Well，這樣便有助於觀察Deep N-Well對於基板雜訊隔離度的影響。再者，於入侵源和接受端之間的保護帶方面，總共設計了三種結構，分別為N/P/N、N/P/N/P/N、N/P/N/P/N/P/N的保護帶結構，在佈局規則可以容許的範圍之下儘可能使三種保護帶的總寬度是一樣的，因為入侵源和接受端之間是P型基板，所以三種保護線在基板雜訊流通的路徑上各自構成了四層、六層、八層的寄生P-N接面電容，這也是主要為了測試較多的P-N接面對於提升基板雜訊隔離度是否有較明顯的助益；最後再將這些保護帶的P型接至Ground端，而N型接至VDD端，以便探討逆向偏壓的寄生P-N接面電容是否也是有助於提升基板雜訊隔離度。 接著在Appendix的部份是高功率橫向擴散電晶體的自熱效應的分析和模型化，基於目前市場上在高壓元件的應用上越來越普遍，但有許多高壓元件的固有弱點尚待提升或解決，諸如元件導通電阻（on-resistance）不夠低、元件安全操作範圍（SOA）不夠廣或是自熱效應的發生太過於嚴重等問題，所以在一開始先引入各種文獻所發表的結構與方式，以及在實際應用上的問題所在。 我們取得了世界先進積體電路公司所提供的元件，這些元件是固定單根Finger的寬度為160(□m)，而變化Finger數目，因為受限於Keithley-4200在Pulse I-V的量測上有總功率的限制，而且元件在較高功率的量測上往往有燒毀的情形，所以在本論文中主要只觀察五種元件，Finger的數目分別是一根、兩根、四根、八根與十六根，以期望能從中得到一些結果。 在本論文的元件建模方面，使用的是HiSIM-HV模型，在第五章中大略地介紹了此HiSIM-HV的模型，並對於所量測的元件進行參數的萃取，再進行自熱效應模型的探討。

In this thesis, we investigated the impact from substrate noise on Si CMOS devices, which is of major concern for high frequency circuits design. Two categories of substrate noise isolation structures were designed and fabricated in 0.18 □m CMOS process to verify the isolation performance and explore the mechanisms responsible for the substrate noise coupling. The experimental results from our test chip can be used to verify the existing models proposed by literatures. The first category of isolation structures are designed for both N- and P- type aggressors or victims in which various guard-rings, such as N-well surrounding P-type aggressor (victim), P-well surrounding N-type aggressor (victim), and P-well/N-well/deep-N-well surrounding N-type aggressor (victim) are adopted to constitute different test structures for verifying two-port isolation capability against substrate noise coupling. Furthermore, four kinds of guard bands like P+, N+/N-well, N+/N-well/deep-N-well, and N+/P-well/deep-N-well/N-well were implemented and allocated between aggressor and victim, trying to enhance the isolation capability but taking area penalty. Also, the distance between the aggressor and guard bands and the total distance between the aggressor and victim are important parameters with trade-off between isolation performance and area consumption. The second category of isolation structures is devised for P-type aggressor and victim in which N-well/deep-N-well is the guard ring used for aggressor and similar structures with or without deep-N-well are adopted as the guard rings for victim. The variation of N-well guard ring with or without deep-N-well can be used to verify any contribution from the deep-N-well to substrate noise isolation in the mentioned test structure with the same type of aggressor and victim. Besides the guard rings, guard bands composed of interdigitated N+ and P+ fingers with 3 different numbers, such as N/P/N, N/P/N/P/N, and N/P/N/P/N/P/N were deployed between the aggressor and victim as a potential solution to enhance the isolation capability. Note that the layouts for N+ and P+, such as width and space are designed to keep the band width the same under varying N+/P+ finger numbers. This kind of layout can help verify if N+/P+ finger numbers is the dominant factor or the isolation capability is limited by the total band width occupied by the multiple N+/P+ fingers. Also, P+ fingers of the guard bands are connected to the ground, while N+ fingers of the guard bands are connected to the VDD, in order to investigate if the increasing P/N junction barrier wider depletion width under reverse bias can help improve substrate noise isolation. One more research topic on high power LDMOS has been covered in this thesis and arranged in the appendix. The test chips were fabricated by 0.25□m, 18V and 24 V LDMOS processes in Vanguard International Semiconductor (VIS) Corporation and our major effort has been focusing on devices characterization and modeling. LDMOS has been known with the advantages of lower cost and easier integration with standard CMOS logic process. However, the conventional LDMOS faces several fundamental problems, such as trade-off between on state resistance (Ron) and off state breakdown voltage (BVoff), current and voltage limitation from self-heating effect, and limited safe operating area (SOA). To tackle the mentioned challenges, high voltage LDMOS characterization for determination of Ron, BVoff, and self-heating effect is the basic work for going to modeling and simulation. Both DC I-V and Pulse I-V measurement can be performed by Keithley-4200 but the power limitation leads to voltage and current compliance, and then the restriction in device total width determined by finger width and finger number. In this thesis, the test devices are limited to fixed finger width (160 □m) and various finger numbers (2~16). HiSIM-HV was employed as the core model and IC-CAP was used as the simulation/extraction tools for model parameters extraction. The models deployed in HiSIM incorporate threshold voltage (VT), mobility, hot carrier effect (HCE) for I-V simulation. Self-heating effect was implemented by thermal resistance, which determine the relaxation for heat transportation and dissipation. Layout dependence of the model parameters will be presented to make the model scalable for LDMOS with various dimensions.