低功耗與超寬頻射頻CMOS混頻器設計與分析

Abstract

本論文利用RF CMOS製程分別設計了應用於無線接收端之超低功耗和超寬頻混頻器。內容主要實現了兩個電路晶片。一個是低功耗混頻器，另一個為超寬頻混頻器。其中低功耗混頻器之設計，採用台積電0.13微米 RF CMOS 製程來實現一個使用折疊式串疊架構的1.4 GHz降頻混頻器，相較於傳統串疊架構可以有效的降低操作電壓，加上電晶體都使用基極順向偏壓技術以降低臨界電壓可進一步降低操作電壓。本設計乃利用此基極順向偏壓技術來達成低功耗電路設計。電源供應系統利用電感電容並聯諧振電路，利用其諧振時的帶通特性，可以將RF操作頻率信號輸入當地載波開關級，而非操作頻率時信號濾除。量測結果顯示，在供應電壓0.3V與1.4 GHz操作下其功耗僅為1.044毫瓦，轉換增益為-6.14 dB，輸入端反射係數皆小於 –18 dB，線性度P1dB為-13 dBm，IIP3為-2.5dBm。各端隔離度皆小於 -22 dB。 超寬頻混頻器之設計，則採用台積電0.18微米 RF CMOS 製程來實現一個使用傳輸線架構的10~55GHz降頻混頻器，相較於傳統架構可以有效的增加頻寬，加上電晶體都當作開關使用，可以節省混頻器主動功率損耗。本設計利用電晶體與傳輸線做搭配，達到高頻寬的輸入反射係數。加上串疊一個電晶體在RF端與LO端，可以獲得更佳的隔離度。量測結果顯示，在供應電壓0.7V操作下其功耗僅為2.1微瓦，並實現10 ~ 55GHz超寬頻，其轉換增益為 -7 ~ -12.3 dB，輸入端反射係數為 -5 ~ -15 dB，線性度P1dB為-1.5 ~ 0 dBm，IIP3為8 ~ 10 dBm。各端隔離度皆小於 -22dB。

Abstract In this thesis, low-power mixer design and fabrication have been realized using RF CMOS technologies for applications in low-power or ultra-wide-band (UWB) wireless receivers. The major achievements are composed of two circuit chips. One is the low-power mixer and the other is ultra-wide-band (UWB) mixer, First, a low-power mixer, the test chip was designed and fabricated in tsmc 0.13 □m RF CMOS process (T13-RF). The low voltage feature is realized by using forward body bias (FBB) technique and folded cascade architecture. In this design, the adoption of FBB is proven successful in reducing MOSFETs’ threshold voltage (VT) and then an aggressive supply voltage (VDD) scaling. The supply voltage system employs a LC tank through which the operational signal at exactly the LC resonance frequency (□0) can pass whereas all the signals other than the resonance frequency will be blocked. The circuit performance measured at 1.4 GHz indicates that power consumption can be reduced to as low as 1.044 mW from ultra-low VDD, down to 0.3V. The conversion gain (CG) achievable under 0.3V and 1.4 GHz is -6.5dB. The input return loss S11 is very low to –18 dB. The linearity corresponding to the available CG is P1dB of –13 dBm and IIP3 of -2.74 dBm. Again, the port to port isolation can be achieved better than -22dB. As for the ultra-wide-band (UWB) mixer, the test chip was designed and fabricated in tsmc 0.18 □m 1.8V RF CMOS process (T18-RF). The ultra-wide-band feature is realized by using transmission line technique. For this down-conversion mixer, an appropriate implementation of transmission line method makes UWB design successful, up to 10~55 GHz. All of the MOSFETs used in this mixer act as switches and this circuit topology contributes to effective reduction of active power. The chip measurement indicates that power consumption can be reduced to as low as 2.1□W from an extremely low VDD, down to 0.7V. The conversion gain (CG) achievable under 0.7V and over wideband 10~ 55GHz is –7 ~ -12.3 dB. The input return loss S11 is –5 ~ -15dB. Good linearity is justified by P1dB of -1.5 ~ 0 dBm and IIP3 of 8 ~10 dBm, corresponding to the mentioned conversion gain. The port to port isolation is better than –22 dB.