考量差動訊號及壓降避免之球閘陣列封裝針腳排列與基板繞線

Abstract

隨著現今超大型積體電路縮小至深次微米技術，使得晶片設計、封裝與印刷電路板的複雜化急遽增加，造成晶片、封裝跟印刷電路板界面間之設計變得更加費時，因此晶片封裝協同設計便成為關鍵且必要的工作。晶片封裝協同設計分成兩個階段，第一個階段為針腳配置，另一個則為基板繞線。針腳配置階段主要是決定訊號在晶片接點銲墊(I/O pad)、銲線(finger)、金屬球凸塊(bump ball)的位置。另一方面，基板繞線則是在封裝基底上將銲線跟對應的金屬球凸塊訊號連接起來。本篇論文針對晶片與封裝之協同設計而提出一個考量差動訊號及壓降避免的針腳指定演算法，並利用修改A*演算法之價值函數來實現基板繞線以增加可繞度及減少繞線層數。實驗結果顯示：在合理的封裝尺寸之下，本篇論文所提出的針腳指定及基板繞線演算法可以有效減少所需繞線層數。

While the advanced very large scale integration (VLSI) circuit is scaling to deep-submicrometer (DSM) technology, the complication in designing chips, packages and the communications between package and board become increasingly significant. The iterative interface design between chip, package and board has been a time-consuming process. As a result, a chip-package-board co-design flow is critical and necessary. The co-design flow contains two stages: one is pin assignment and the other is package substrate routing. The pin assignment is to determine the location of I/O signals, fingers and bump balls on ball gird array (BGA) packages. On the other hand, the package substrate routing is to connect each finger with its corresponding bump ball by wire segments. In this thesis, we have proposed a new pin assignment algorithm for the chip-package-board co-design flow considering the differential pair signals and IR-drop. We also have applied a modified A* algorithm to implement the substrate routing which increases the routability and reduces the total number of layers. The experimental results show that our methodologies can effectively reduce the number of layers while controlling package size to be a reasonable one.