晶片上連線設計與驗證之研究

Abstract

隨著數位系統的功能日趨複雜，將會需要整合更多的智材(IP)到單一晶片之中，晶片上各模組間相互傳遞資料時所需之傳輸頻寬亦大量增加，且其互動行為將極為複雜，使得設計一個能符合系統各項需求之通訊架構成為一項相當困難的挑戰。另一方面，製程上的進步雖然讓單一晶片得以容納更多、切換速度更快的的電晶體，但晶片上未能隨著製程之特徵尺寸(feature size)縮短的全域性連線(chip-scale wires)，其訊號傳遞所需的時間將超過一個、甚至多個系統時脈週期的現象，使得通訊架構之設計更加困難。可以預見的是，未來若系統沒有很好的通訊架構設計及驗證方法，將很難保證最終實作晶片之成功率。 在實現晶片的通訊架構上，其選擇可以從傳統分享式匯流排(shared bus)到最先進的單晶片網路系統(Networks-on-chip)，其中分享式匯流排之實現最為直覺及單純，但它通常只能提供非常有限的頻寬供系統使用；而單晶片網路系統雖然有著頻寬充沛的優點，也可能成為未來複雜之數位系統廣為採用的通訊架構之一，但其最佳化時所需考量的參數，以及所涉及的層面非常複雜，以致設計不易，且它的發展尚屬萌芽階段。因此在本論文中，我們採用另一種名為匯流排矩陣(bus matrix)的通訊架構，不但可以提供比分享式匯流排更多的頻寬，設計複雜度及所需之額外硬體也比單晶片網路系統較低。而針對接線多時脈週期訊號延遲的問題，延遲不敏性(latency-insensitive)的先進設計概念提供了一個實際的解決方案，基於此概念，我們提出了一個使用匯流排矩陣實現通訊架構的高抽象層級(high abstract level)設計方法，同時在考量晶片佈局(floorplan)之下，使得系統效能在後段設計流程中仍然能被滿足。 另一方面，在系統逐步地被實現成晶片的過程中，晶片上組成模組之介面終究會成為許多單一位元(pin-accurate)接腳的連接埠(port)，並透過許多的連接線(wire)彼此連接。現今的系統很可能就會有上萬、或甚至更多的連接埠需要彼此相連，若要以人工的方式驗證這些連接埠的接線是否正確，將會是一項非常困難且極容易出錯的工作。因此在本論中，我們針對系統中單一位元接腳的連接埠提出一個新的接線模型(connection model)及其相對應之錯誤模型(error model)。基於這些模型，我們發展了一個能產生最少之驗證向量組(pattern set)的演算法，以及一個驗證接線正確性的驗證流程。一旦系統中各模組的介面成為單一位元的抽象層級，本驗證方法及流程即可被立即應用。 透過本論文中的二項研究，可以得到一個符合系統需求之匯流排矩陣通訊架構，同時減少因為接線錯誤所可能導致多餘的設計流程迴圈(design iteration)。

As modern digital systems get more complex, more IPs will be integrated in a single chip as well. The dramatically increased on-chip bandwidth requirement and the extremely complex and unpredictable communication behavior make designing communication architectures a difficult task. Moreover, it would be even more challenging when signal propagation delay on the interconnect wires inevitably exceeds one or several clock cycles as the process technology keeps advancing. Since on-chip global wires do not shrink with the feature size of process as what transistors and local wires do. Having all necessary IPs only can no longer guarantee a successful chip, without communication architectures being carefully designed and verified. There are many communication architecture choices, from conventional shared buses to state-of-the-art networks-on-chip. Shared bus-like architectures are simple to implement but can only provide limited bandwidth. Networks-on-chip can provide abundant bandwidth but its implementation involves too many optimization dimensions and is still in its infancy, though it is foreseeable a good candidate for future complex systems. An alternative architecture, bus matrix, is adopted in our work because it can provide much higher bandwidth capability than shared buses and much less design overhead and complexity than network-on-chip. In addition, to conquer the problem that signals on the interconnection can take multiple clock cycles for propagation, we also adopt the advanced concept of latency-insensitive design methodology, which is one of the promising solutions. Based on the concept, we propose a high level design methodology to obtain the optimal bus matrix for an application-specific system and at the same time sustain its performance in the following physical implementation flow by taking floorplanning into consideration. On the other hand, when implementation details are gradually added to a design, the interfaces of modules will be eventually refined to pin-accurate and the interconnections will become single-bit wires connecting the ports on the interfaces. The number of ports could be in the degree of tens of thousands or more when a system is complex enough. To manually verify if these ports are connected correctly is nearly impossible and error-prone. In this dissertation, we present a new connection model and the corresponding error model for pin-accurate port connections. Based on the models, we propose an algorithm capable of generating the minimum pattern set, a methodology for diagnosing errors, and a verification flow used to verify port connections. The methodology can be applied to verify the port connections as soon as the interfaces in a system are refined to pin-accurate. We believe that the quality of communication architecture can be enhanced and possible design iterations due to incorrect port connections can be also reduced through the methodologies studied in this dissertation.