標題: | 二次微分與積分技術且使用小的串聯等效阻抗輸出電容應用於雙電壓控制架構 Quadratic Differential and Integration Technique in V2 Control Buck Converter with Small ESR Capacitor |
作者: | 王士榮 Wang, Shih-Jung 陳科宏 Chen, Ke-Horng 電控工程研究所 |
關鍵字: | 二次微分與積分技術;雙電壓控制架構;低串聯等效阻抗輸出電容;Quadratic Differential and Integration Technique;V2 Control Buck Converter;Small ESR Capacitor |
公開日期: | 2008 |
摘要: | 隨著電子可攜式產品的快速發展與進步,提供穩定而且無雜訊的電源對電源管理IC來說已經是一個越來越重要的目標。此外許多產品在使用上為了降低能量消耗而設定了許多模式,例如待機模式。因此,在不同模式之間的轉換中,電源對於不同負載轉換的暫態反應就顯得更為重要。傳統雙電壓控制架構就提供了一個得到非常好的暫態反應的方法,但是此架構必須要使用極大的串聯等效阻抗輸出電容來得到電感電流的資訊。如此一來,將會造成大的輸出電壓漣波並可能影響到後方應用電路的表現。
本論文實現了二次微分與積分技術且使用小的串聯等效阻抗輸出電容應用於雙電壓控制架構,且以台灣積體電路製造股份有限公司點三五微米互補式金氧製程來實現。利用二次微分與積分技術,內部訊號將可以不受到輸出串聯等效阻抗大小的影響,因此可以大幅的減小輸出電容所需要的串聯等效阻抗,同時也能夠讓輸出電壓漣波降到最低。此外,此技術並不會影響到原本雙電壓控制架構快速暫態反應的優點。經過迴路分析可知此電路再加上PI補償器後可以達到完全的極零點相消補償,使的整個系統相當穩定。晶片量測結果顯示本論文實現之電路輸出電壓漣波遠小於傳統雙電壓控制架構,而300 mA負載變動發生的輸出電壓變動小於40 mV,電壓回穩的反應時間繼承傳統雙電壓控制快速反應的優點小於9 μs。最後,整體的能量轉換效率最高能達到93 %。 With the advance of the portable device, to supply a stable and noiseless source has become a more and more important issue of power management module. Besides, some operation mode as idle is designed to economic the power consumption. That means the power management should response rapidly between the modes change. To overcome demand, the V2 control structure has been widely used because of the fast transient response. However, the conventional V2 control requires large ESR of the output capacitor and that would cause large output voltage ripple which would affect the performance of applications. This thesis proposes a quadratic differential and integration (QDI) technique for the design of V2 control buck converters with small equivalent series resistance (ESR) of the output capacitor. The QDI technique, which eliminates the use of large ESR in the V2 control structure, achieves the fast transient response with the small output voltage variation in transient period. Besides, the precise sensing signal is derived from the QDI circuit without the unwilling ESR-related distortion. Moreover, the loop analysis demonstrates that the proposed QDI circuit and the PI compensator can generate the compensation zero pair to stabilize the system. Experimental results show that the output voltage has small voltage ripple opposite to the conventional V2 control. In load transient period, the overshoot/undershoot voltage is smaller than 40 mV, and the transient recovery time inheriting the advantage of V2 control is shorter than 9 μs of a 300 mA load step. The highest full chip power conversion efficiency is about 93 %. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079612524 http://hdl.handle.net/11536/41841 |
顯示於類別: | 畢業論文 |