低溫複晶矽薄膜電晶體穩定性分析與缺陷效應探討

Abstract

近幾年來液晶顯示器由於需求量大，許多研究單位與公司紛紛投入研發新技術，造成顯示功能上的功能日新月異，從單純的顯示與投影功能，到目前正夯的觸控螢幕，以及未來夢想顯示器：SOP(system on panel)，也就是將系統功能與面板直接整合在一塊玻璃上。在目前市面上主要以非晶矽薄膜電晶體為主流，多晶矽薄膜電晶體則因為成本上考量，市占率偏低。然而非晶矽薄膜電晶體缺乏P型以及傳輸速率太低的問題和高電壓驅動，並不適合拿來在電路應用上；而多晶矽薄膜電晶體則同時擁有P型與N型結構能夠做出CMOS結構，加上傳輸移動率(mobility)高，目前在面板上的周邊電路已經有一些應用。 本論文的研究動機主要是因為多晶矽薄膜電晶體不管在數位或是類比電路上會有閘極偏壓造成原件裂化問題，在加上玻璃導熱速率很差會面臨高溫的影響，因此必須要同時結合閘極偏壓與溫度變化的影響。此外在操作情形下的元件壽命長短也必須考量。 在此我們討論兩種型態P型TFT與N型TFT分別在閘極正偏壓與負偏壓的情況下，此時汲極與源極接地，以及在各種不同溫度與時間下，探討元件裂化情形差異，這裡跟傳統MOSFET中的NBTI(Negative Bias temperature instability)與PBTI(Positive Bias temperature instability)類似，只是差在較高的溫度與電壓。 我們會先探討NBTI對PTFT的影響，我們把溫度、電壓與時間對臨界電壓的關係，用一個簡單數學式子描述之，並且將公認的p-MOSFET的NBTI理論引進來物理解釋，然而多晶矽薄膜電晶體多了晶體界面(grain boundary)的影響，因此有必要把它納入考量。之後再把PBTI對NTFT、PBTI對PTFT與NBTI對NTFT的現象做一一的解釋與比較。 另外我們會針對缺陷的形式與量做進一步分析，過程中包含了一般對IV curve基本電性分析、CV的分析以及從IDVG曲線中萃取晶界與介面缺陷多寡；另外引進了Gated PIN結構的TFT，它同時擁有電子源與電洞源，可以讓我們實行電荷幫浦(charge pumping)量測，利用這技術可以更進一步了解介面缺陷的形式(donor or acceptor)與定性定量分析。 最後，將四種組合各自的劣化機制徹底的統整與分析，區分各自的劣化機制。

As the large demand of liquid crystal display in recent years, many research organization and corporation have invest in new technique. So the function of display changes with each passing day, from simple display and projection to the popular touch panel at the present day. The ideal dream of display is one combined with system package and panel on a glass which is so called SOP (system on panel). Now the amorphous silicon thin-film transistor is the main flow on business situation. Polycrystalline thin-film transistor has low market share for high cost. But amorphous thin-film transistor has problem of only N-type and the slow mobility, it is unsuitable for circuit application. For Polycrystalline thin-film transistor, it has the P-type and N-type for CMOS circuit composition. Moreover, the carrier mobility is much fast than a-Si. Now, some peripheral circuit has fabrication on panel with poly-Si. In this thesis, the motivation is because poly-Si TFT for circuit application whether digital or analog circuits will face to gate bias stress induced degraded problem on circuit working. And the panel’s poor thermal conductance will caused high temperature. Therefore, the degrade influence combines with gate bias and temperature. The life time of device on operation has to be concerned. We discuss two type of TFT：N and P at positive and negative gate bias and source drain ground condition. And then at different temperature and time we confer the different degrade phenomenon. This is like NBTI(Negative Bias temperature instability) and PBTI(Positive Bias temperature instability) in conventional MOSFET, just the difference of higher temperature and stressed voltage. We discuss the influence of NBTI on PTFT. Using a simple mathematical formula describes the correlation of threshold voltage, temperature, voltage and time. And explanting it by acknowledged NBTI on p-MOSFET theory. However, the polycrystalline has not only interface of silicon dioxide and polycrystalline but also grain boundary, so it is necessary to concern grain boundary for degradation. Afterward, phenomenon of PBTI on NTFT, PBTI on PTFF and NBTI on NTFT is explained and compared one by one. Besides, we further analyze the type and quantity of defect. In the measure process, it involves commonly basic electric analysis for IV curve, CV analysis and extracts the traps amount of grain boundary and interface from IDVG curve. Additionally, we introduce the gated PIN diode which has electron source and hole source, using the PIN structure, we can use charge pumping measurement. This technique can further understand the type (donor or acceptor) and qualitative and quantitative analysis. Finally, thoroughly comparing and analyzing the degrade mechanism of the four conditions and distinguishing each degrade mechanism.