垂直型氧化物薄膜電晶體技術之研究

Abstract

在本論文中，我們成功發展出垂直通道結構的非晶系銦鎵鋅氧薄膜電晶體，其通道長度只有五百奈米。經由對此垂直通道結構的元件做電特性分析，其電流開關比大於十的六次方倍。在垂直電晶體的元件結構中，源極和汲極之間是藉由一層絕緣層的厚度來決定通道長度。為了確認此元件垂直結構的正確性，我們使用掃描式電子顯微鏡對其做結構剖面的分析。我們藉由互換源極跟汲極電壓的方式量測元件以探討此不對稱結構以及電極接觸特性。此外，我們也發現在沉積閘極介電層的同時也會對主動層界面形成缺陷而造成其電特性不理想以及可靠度不佳等問題。最後，我們也對此元件做閘極偏壓可靠度和光響應可靠度這兩方面的分析。在正偏壓可靠度部份，臨界電壓隨著時間增加會往負的方向做些許的偏移；在負偏壓可靠度部份，臨界電壓最終會往正的方向偏移4.1伏特當給的偏壓時間達到120分鐘。而此元件本身臨界電壓在光響應可靠度分析下幾乎不變，所以其抗光性極佳。

We had successfully realized vertical-channel amorphous IGZO thin film transistors with submicron channel length (500nm). The device performance of the fabricated V-TFT was evaluated with the characteristics of Ion/Ioff current ratio greater than 106. The source and drain were separated by a insulator for V-TFTs, it meaned that the thickness of this insulator decided the channel length. The structure analysis of scanning electron microscopy was implemented to confirm the vertical structure of the TFT. We study the asymmetric structure and the electrode contact properties by switching the source and drain as we measuring the device performance. Besides, we find that the defects appeared in the a-IGZO channel region in deposition process of the PECVD SiO2 gate dielectric. This is the reason for non-optimum device performance and reliability. Finally, the reliability analysis for the V-TFTs was applied such as gate bias stress and light illumination sensitivity. The PGBS reliability analysis for our devices exhibits some negative threshold voltage shifts as the stress time increase, and the NGBS reliability analysis for that exhibits positive threshold voltage shifts to 4.1V as the stress time increase to 120 min. In terms of photo-reliability, the device is not sensitive to the environmental light, so it has nice resistance to light.