具粗糙穿隧氧化層及阻障氧化層SONOS記憶體之研究

Abstract

本論文主要探討透過氧化非晶矽層以提高SONOS記憶體之表面粗糙度，進一步提升記憶體寫入速度。在沉積氧化層之前，先沉積一層非晶矽，再將其完全氧化形成穿隧氧化層或阻障氧化層。在氧化過程中，非晶矽由於存在許多晶界(grain boundary)使氧容易快速經由晶界擴散，導致非晶矽中晶界處的矽氧化速率高於矽晶粒內，得到氧化層厚度不均勻的結果，實驗中以原子力顯微鏡(atomic force microscopy, AFM)及穿透式電子顯微鏡(transmission electron microscopy, TEM)檢視氧化層表面之不平整現象。此厚度不均勻之氧化層在閘極跨壓下會產生局部的電場加強效應(local field enhancement)，提升記憶體之Fowler-Nordheim穿隧效率並縮短寫入時間以及增加寫入電壓窗(program window)。實驗分為兩個部份，第一部份為應用粗糙介面至穿隧氧化層，電子在此種裝置中由矽基板寫入；第二部份為應用粗糙介面至阻障氧化層，並透過閘極注入電子寫入。 第一部份分別用N2O及O2作為氧化氣體氧化非晶矽形成通道氧化層，並以氮化矽及TEOS分別作為電荷捕陷層及阻障氧化層。形成元件後比較寫入速度，表面粗糙的穿隧氧化層得到較一般熱氧化層高的寫入速度及不錯之記憶能力。在W/L=5μm/10μm之元件上以13V閘極跨壓寫入1秒之時間，N2O氧化層可得3V之記憶窗，O2氧化層可得1.9V之記憶窗，一般熱氧化層僅0.6V之記憶窗。元件尺寸大小會顯著影響此類元件之寫入速度，面積越大則寫入速度越快。載子儲存能力在攝氏200度高溫下經104秒後N2O及O2皆能維持1.8V之記憶窗。閘極多晶矽之摻雜種類亦影響記憶能力，使用P+摻雜較N+在記憶窗上有0.25V之明顯提升。 第二部份之元件先以N2O熱氧化矽基板作為穿隧氧化層及沉積氮化矽做為電荷捕陷層，之後分別以90秒及120秒的時間沉積非晶矽，並以溼式氧化過氧化之形成阻障氧化層。結果顯示閘極跨壓為-17V經過1秒的寫入時間後，非晶矽沉積時間為90秒之寫入電壓窗是2.3V，相較於對照組以TEOS作為阻障氧化層之寫入電壓窗僅0.7V。載子儲存能力方面，非晶矽沉積時間為90秒之元件在攝氏200度下經過104秒後，原先2V的記憶窗下降了0.6V。我們發現利用內嵌矽奈米晶體於氮化矽以及使用N2O緻密化阻障氧化層，有助於修復此記憶能力不佳的現象。

In the thesis, we proposed a SONOS memory with faster program speed by using oxidation of amorphous silicon as rough tunnel oxide and blocking oxide. Before oxidizing, we deposited an amorphous silicon layer and then fully oxidized this layer into rough tunnel oxide or blocking oxide. In the process of oxidizing, the oxygen diffused faster through the grain boundary of poly-silicon than inside the grain. This phenomenon caused faster oxidation rate at the grain boundary and resulted in rough oxide surface. We also examined this rough surface by atomic force microscopy (AFM) and transmission electron microscopy (TEM). When applying a gate voltage across rough oxide, the electric field would increase significantly at the oxide pinpoints due to local field enhancement. This effect would promote the Fowler-Nordheim tunneling efficiency, program speed and program window. The experiment diverges into two parts. In part one, we applied this rough oxide to form the tunnel oxide of SONOS memory which electrons are injected from silicon substrate. In part two, we applied the rough oxide to form blocking oxide of SONOS memory which electrons injected from gate when applying a negative gate bias. In part one, N2O and O2 were used as oxidizing ambient forming rough tunnel oxide. Nitride and TEOS were used to form trapping layer and blocking oxide, respectively. As result shown, devices with rough tunnel oxide has significant fast program speed. The program window of N2O, O2 and control devices of W/L=5μm/10μm under 13V gate voltage after 1 second programming are 3V, 1.9V and 0.6V, respectively. The dimension of rough devices also affects the program speed, devices program faster in larger dimension. The retention of rough devices has shown that the window retains 1.8V under 200°C baking after 104 seconds. The doping type of poly-silicon gate also affects the memory retention, the window of P+ doping remained 0.25V higher than N+ doping after baking. In part two, the tunnel oxide and trapping layer were prepared by N2O oxide and nitride, respectively. Then amorphous silicon layers were deposited, with 90-second or 120-second deposition time as a split. Wet oxide was used to over-oxidize this film to form rough blocking oxide. The program windows of 90-second and TEOS control devices under -17V gate voltage after 1 second are 2.3V and 0.7V, respectively. The memory window of 90-second device has dropped from 2V to 1.6V under 200°C baking after 104 seconds which is not good. We discovered that embedded silicon nano-crystals into nitride trapping layer and N2O densification of blocking oxide are two good ways to recover the retention of the rough blocking oxide devices.