完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | YANG, YH | en_US |
dc.contributor.author | WU, CY | en_US |
dc.date.accessioned | 2014-12-08T15:05:45Z | - |
dc.date.available | 2014-12-08T15:05:45Z | - |
dc.date.issued | 1989-10-01 | en_US |
dc.identifier.issn | 0956-3768 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/4288 | - |
dc.language.iso | en_US | en_US |
dc.title | ANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATES | en_US |
dc.type | Article | en_US |
dc.identifier.journal | IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS | en_US |
dc.citation.volume | 136 | en_US |
dc.citation.issue | 5 | en_US |
dc.citation.spage | 245 | en_US |
dc.citation.epage | 254 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:A1989AV51700003 | - |
dc.citation.woscount | 1 | - |
顯示於類別: | 期刊論文 |