矽化鎳及鍺化鎳之金屬閘極在電晶體上的研究

Abstract

由於多晶矽本身的特性符合現今閘極製造技術，因此以它當作電晶體閘極電極材料己長達數十年的時間。然而，當元件尺寸縮微到100奈米層級時，以多晶矽為閘極技術的一些問題則日趨嚴重，像閘極空乏和硼會穿隧氧化層進入到通道中之效應。使用金屬來當做閘極電極也許是解決上述問題的唯一方法，以金屬材料做為閘極不但可解決閘極空乏和硼穿隧氧化層等效應，且可大大的降低閘極電阻值。 我們分別製造矽化鎳及鍺化鎳之金屬閘極在N型及P型電晶體上，以1.9奈米厚之氧化矽或為其閘極介電質，其經由平帶電壓所粹取之功函數分別為4.55及5.2電子伏特，符合ITRS所宣稱要求的功函數。新發展出來的鍺化鎳閘極有著與矽化鎳相同的低溫製造優點。在我們的量測結果中，發現閘極空乏的現象並沒有發生是我們形成全金屬矽化物證據，此外，其電子、電洞的移動力亦達到標準元件移動力的水準。 在傳統的電晶體結構中，使用高介電係數介電質來當作閘極介電質也是電晶體縮微的趨勢之一。但臨界電壓的位移及電子移動力下降等現象已被發現並提出，可能是由於高介電係數介電質和多晶矽在介面的不相容特性而造成，因此，高介電係數氧化鋁/矽及以矽化鎳和鍺化鎳為金屬閘極之元件也被一併製作來做比較。在低溫不超過500度的製程環境相當適合於高介電係數介電質的整合，以利於減少介面的反應、介電質的結晶，及氧分子穿隧介電質和矽基板之介面。

Since the characteristic of poly-silicon is suitable for gate electrode in current VLSI technology, it has been used as the MOSFET gate material for decades. However, as MOS devices are scaled into the sub-100 nm regime, poly-Si gate technology issues such as gate depletion and boron penetration become more problematic. Using the metal as gate electrode may be the only one gateway to solve these problems. A metal gate material not only eliminates the gate depletion and boron penetration effects, but also greatly reduces the gate sheet resistance. We have fabricated the fully silicided NiSi and germanided NiGe dual gates N- and P-MOSFETs on 1.9 nm thick SiO2 gate dielectric. The extracted work functions of fully NiSi and NiGe gates were 4.55 and 5.2 eV respectively, which was corresponds to the International Technology Roadmap for Semiconductors (ITRS) requirements of work function for N- and P-MOSFET. The newly developed fully germanided NiGe gate has the same advantage of its low temperature formation as fully silicided NiSi. In our measurement, poly depletion effect phenomenon was not observed which is the evidence of fully silicide or germanide was formed. Additionally, the fully silicided NiSi and germanided NiGe gates MOSFETs show electron and hole mobilities close to universal mobility model values. Using high-κ dielectric as gate insulator is also the scaling trend for traditional MOS structure. Shifting threshold voltage and degrading electron mobility phenomenon were observed and proposed in many literatures since high-κ dielectrics and polysilicon gates were incompatible in their interface. Therefore, high-κ Al2O3/Si n- and p-MOSFETs with fully silicided NiSi and germanided NiGe dual gates are also fabricated for comparing. The low process of maximum 500oC RTA is ideal for high-κ gate dielectric integration to minimize the interface reaction, high-κ crystallization, and oxygen penetration in high-κ/Si MOSFETs.