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dc.contributor.author楊學人en_US
dc.contributor.authorHsueh-Jen Yangen_US
dc.contributor.author張國明en_US
dc.contributor.author桂正楣en_US
dc.contributor.authorKow-Ming Changen_US
dc.contributor.authorCheng-May Kweien_US
dc.date.accessioned2014-12-12T01:32:24Z-
dc.date.available2014-12-12T01:32:24Z-
dc.date.issued2003en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009111549en_US
dc.identifier.urihttp://hdl.handle.net/11536/43124-
dc.description.abstract本篇論文中,我們對具有超薄非晶矽層之準分子雷射退火(excimer laser-annealed)低溫複晶矽薄膜電晶體之特性做了一系列的研究與比較,在不需要額外的光罩下,藉著覆蓋一層超薄非晶矽層,不僅降低了雷射退火通道之表面粗糙度也使開/關電流的比值改善了約一個數量級; 另外,也進一步的抑制了扭節現象的產生。我們發現到超薄非晶矽的最佳覆蓋厚度為5nm; 研究結果顯示,開/關電流之比值在汲極電壓為5V時可從4.15 x 104提升至3.45 x105,臨界電壓輕微的偏移到2.43V,通道表面粗糙度之方均根(RMS)可改善至8.52nm,除此之外,和傳統結構的薄膜電晶體(無超薄非晶矽層)相比,此新穎結構具有較佳的熱電子應力承受能力。zh_TW
dc.description.abstractIn this thesis, the characteristics of excimer laser annealed low temperature polycrystalline silicon TFT's with/without an ultra-thin a-Si layer have been investigated and compared. With capping an appropriate ultra-thin a-Si layer, the surface roughness of laser-annealed channel is not only decreased, but also the On/Off current ratio is improved about one order without extra mask step and kink effect is further suppressed. We also find that the optimum thickness of capping ultra-thin a-Si layer is about 5-nm. In our study, the On/Off ratio is rose from 4.15 x 104 to 3.45 x 105 for Vds = 5 V, Threshold voltage slightly shift to 2.43 V and RMS surface roughness of channel can be improved to 8.52-nm. And it has better hot-carrier stress endurance than conventional TFTs without an ultra-thin a-Si layer.en_US
dc.language.isoen_USen_US
dc.subject薄膜電晶體zh_TW
dc.subject雷射退火zh_TW
dc.subject非晶矽zh_TW
dc.subject複晶矽zh_TW
dc.subjectThin-film transistorsen_US
dc.subjectLaser-annealeden_US
dc.subjectAmorphous siliconen_US
dc.subjectPolycrystalline siliconen_US
dc.title具有超薄非晶矽層之高效能雷射退火複晶矽薄膜電晶體之製作與特性研究zh_TW
dc.titleThe Fabrication and Characterization of High Performance Laser-annealed Polycrystalline Silicon Thin-Film Transistors with an Ultra-Thin Amorphous-Silicon Layeren_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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