以階層為基礎插入緩衝器的時鐘樹合成

Abstract

隨著大型積體電路設計製程持續地縮小，現今時鐘網路合成不僅考慮維持零延遲特性，也同時考慮障礙物處理、過長線長造成的迴轉率問題（Slew problem）和製程變異。因此，時鐘網路合成變得複雜且喚起對健全的時鐘網路建造演算法的緊急需求。[20]中的時鐘網路合成(Clock network synthesis)提出一個完整的時鐘樹設計，並且在降低時鐘延遲範圍(Clock latency range)得到漂亮的成果。在此，我們加強前述方法避開障礙物和降低延遲變異兩方面的能力。首先，以群組為基礎的避開障礙物時鐘樹繞線在有障礙物隨機分佈的電路上有良好表現，而且比未做之前少了31％的時鐘延遲範圍。它同時也有較高的完成率。論文中所提出的層次插入並聯緩衝器以及決定線路大小演算法在插入緩衝器階段明顯地縮小了延遲差異（Delay variation），而且花費的時間是原來的兩倍快。實驗結果說明我們比起ISPD 2009年時鐘網路合成競賽的優勝者，降低了42％的時鐘延遲範圍，但是並沒有消耗較多的能源。這些改進有效地使[20]中的時鐘樹合成流程更加完整。

As the manufacturing process in VLSI design technology continues to shrink, clock network synthesis nowadays considers not only keeping zero-skew property but also issues such as blockage handling, slew problems caused by long wires and process variation. Thus, clock network synthesis becomes complex and arouses urgent needs for robust construction algorithm. The clock tree synthesis in [20] addressed an integrated clock tree design and had elegant achievements on minimizing clock latency range. Herein we enhance the previous work in respect to obstruction avoiding and delay variation minimizing. First, group-based obstacle-avoiding clock tree routing performs well on circuits with randomly distributed obstructions and has 31% less clock latency range than before. It also gives higher completion rate. The proposed level parallel buffer insertion and wire sizing minimizes delay variation impressively at buffering stage and runs 2× faster than previous method. Experimental results reveal that this work is 42% smaller clock latency range than winners in the ISPD’09 clock tree synthesis contest but does not consume much power. The improvements consolidate the clock tree synthesis flows in [20] effectively.