標題: | 考慮降低臨界面積的無格點線軌繞線與層指派 Girdless Track Routing and Layer Assignment for Critical Area Reduction |
作者: | 李育維 Lee, Yu-Wei 李毅郎 Li, Yih-Lang 資訊科學與工程研究所 |
關鍵字: | 實體設計自動化;關鍵面積;無格點線軌繞線;層指派;良率導向設計;製造導向設計;Phsyiscal Design Automation;Critical Area;Gridless Track Routing;Layer Assignment;Design for yield;Design for Manufacturbility |
公開日期: | 2009 |
摘要: | 近來對於為製造而設計(DFM,Design for manufacturing)的關注度正持續的提高。其中一個被大量討論與研究的議題就是隨機瑕疵(Random defects)產生的臨界區域(Critical area)的計算與抑止。由於隨機瑕疵不隨著製程縮小,降低隨機瑕疵產生錯誤的機率與其衍生影響已成為在先進製程中提高良率的關鍵要素之一。其中,調整與排列線路已被證明是一可有效降低設計對隨機瑕疵的敏感度的方法。在設計流程中,線軌繞線(Track routing)因可快速的排列實體的線路,已被認定是一考慮DFM因素的理想階段。除了線軌繞線外,層指派(Layer assignment)也被認為是一個有潛力考慮DFM因素的步驟。
本論文提出了一個整合無格點(Gridless)線軌繞線法與n層指派法並考量隨機瑕疵影響的方法(RAAT) 。此論文首先定義了考慮障礙物層指派與對錯誤機率友善的線路排序等兩問題。利用傳統用於擺置(placement)的方法如最少切量分群法(Min-cut partitioning),RAAT可以快速並有效地排列與指派線路。實驗結果顯示了整合層指派與線軌繞線的重要性。同時,與前人的成果相比,RAAT提高不只可更快速地完成大部分情況的繞線,也具有更高的完成率,並可以在蒙地卡羅模擬(Monte Carlo simulation)中至多降低約10%的錯誤發生。 An increasing interest has been drawn in the design for manufacturing (DFM) problems. One of the heavily surveyed DFM problems is the formulation and reduction of critical area for random defects. The effect of random defects, which do not shrink with the manufacturing process, has become one of the key yield-related factors in advanced processes. In order to improve the sensitivity to random defects, arranging interconnects has been proven to be an effective approach. Among the design flow, track routing is an ideal stage for DFM issues because it quickly arranges physical interconnects to proper locations. Other than track routing, layer assignment has also found to be a promising step for DFM issues. This paper proposes an integration of gridless track routing and layer assignment with random defect awareness, RAAT. Two problems has been defined in this work, which are the obstacle-aware layer assignment and the POF (probability of failure)-friendly wire ordering. Utilizing conventional approaches used for placement and floorplanning like min-cut partitioning, RAAT could arrange and assign interconnects efficiently. Experimental results show the necessity of the integration of layer assignment and track routing. Meanwhile, RAAT could not only finish each case quickly but also achieves higher completion rate. In addition, RAAT also reduces 10% of the number of failure at most in Monte Carlo simulation compared to previous works. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079655617 http://hdl.handle.net/11536/43424 |
顯示於類別: | 畢業論文 |