高能源效率可重組基本運算單元之設計與實現

Abstract

在本論文中，我們提出了一個高能源效率可重組的浮點數基本運算單元。此基本運算單元提供了16位元除法、16位元除以開根號、16位元對數、16位元指數、32位元倒數、32位元開根號倒數、32位元對數、32位元指數的運算。我們運用了一個分段線性近似法來計算16位元倒數、開根號倒數、對數、指數運算，再配合乘法完成16位元除法與16位元除以開根號；我們提出一個新的向前看牛頓–拉福生法去計算32位元倒數及開根號倒數，以及二次方近似法來計算對數及指數。模擬顯示16位元和32位元的運算精確度都可以達到接近1ulp。此提出基本運算單元使用TSMC 0.18um製程設計與實現，模擬顯示操作在166 MHz時脈下，相較於32位元基本運算所需的平均功耗，其16位元基本運算所需的平均功耗可以節省69.4%。

In this thesis, a power-efficient reconfigurable floating-point elementary function unit is proposed. According to application requirement, the proposed unit can support 16-bit division, 16-bit divide-by-square-root, 16-bit logarithm, 16-bit exponential, 32-bit reciprocal, 32-bit inverse square root, 32-bit logarithm, and 32-bit exponential operations. The presented elementary function unit employs a piecewise linear approximation scheme for 16-bit operations, the proposed relaxed look-ahead Newton-Raphson method for the computation of 32-bit floating-point reciprocal and inverse square root, and a quadratic approximation for 32-bit logarithm and exponential. All the operations have a maximum error near 1ulp. The proposed power-efficient reconfigurable elementary function unit in TSMC 0.18um CMOS process can be operated at 166MHz. Compared with four 32-bit elementary functions, the four 16-bit elementary functions can achieve the power reduction by 64.9% on average.