标题: 高能源效率可重组基本运算单元之设计与实现
A Power-Efficient Reconfigurable Elementary Function Unit Design and Implementation
作者: 张庭维
Chang, Ting-Wei
范伦达
Van, Lan-Da
资讯科学与工程研究所
关键字: 基本运算单元;可重组;向前看牛顿法;Elementary Function Unit;Reconfigurable;Look-ahead Newton-Raphson
公开日期: 2009
摘要: 在本论文中,我们提出了一个高能源效率可重组的浮点数基本运算单元。此基本运算单元提供了16位元除法、16位元除以开根号、16位元对数、16位元指数、32位元倒数、32位元开根号倒数、32位元对数、32位元指数的运算。我们运用了一个分段线性近似法来计算16位元倒数、开根号倒数、对数、指数运算,再配合乘法完成16位元除法与16位元除以开根号;我们提出一个新的向前看牛顿–拉福生法去计算32位元倒数及开根号倒数,以及二次方近似法来计算对数及指数。模拟显示16位元和32位元的运算精确度都可以达到接近1ulp。此提出基本运算单元使用TSMC 0.18um制程设计与实现,模拟显示操作在166 MHz时脉下,相较于32位元基本运算所需的平均功耗,其16位元基本运算所需的平均功耗可以节省69.4%。
In this thesis, a power-efficient reconfigurable floating-point elementary function unit is proposed. According to application requirement, the proposed unit can support 16-bit division, 16-bit divide-by-square-root, 16-bit logarithm, 16-bit exponential, 32-bit reciprocal, 32-bit inverse square root, 32-bit logarithm, and 32-bit exponential operations. The presented elementary function unit employs a piecewise linear approximation scheme for 16-bit operations, the proposed relaxed look-ahead Newton-Raphson method for the computation of 32-bit floating-point reciprocal and inverse square root, and a quadratic approximation for 32-bit logarithm and exponential. All the operations have a maximum error near 1ulp. The proposed power-efficient reconfigurable elementary function unit in TSMC 0.18um CMOS process can be operated at 166MHz. Compared with four 32-bit elementary functions, the four 16-bit elementary functions can achieve the power reduction by 64.9% on average.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079655625
http://hdl.handle.net/11536/43432
显示于类别:Thesis