| 標題: | PHYSICAL TIMING MODELS OF SMALL-GEOMETRY CMOS INVERTERS AND MULTI-INPUT NAND NOR GATES AND THEIR APPLICATIONS |
| 作者: | WU, CY HWANG, JS 電子工程學系及電子研究所 電控工程研究所 Department of Electronics Engineering and Institute of Electronics Institute of Electrical and Control Engineering |
| 公開日期: | 1-Jun-1989 |
| URI: | http://hdl.handle.net/11536/4344 |
| ISSN: | 0038-1101 |
| 期刊: | SOLID-STATE ELECTRONICS |
| Volume: | 32 |
| Issue: | 6 |
| 起始頁: | 449 |
| 結束頁: | 467 |
| Appears in Collections: | Articles |
- NEW FAST FIXED-DELAY SIZING ALGORITHM FOR HIGH-PERFORMANCE CMOS COMBINATIONAL LOGIC-CIRCUITS AND ITS APPLICATIONS / HWANG, JS;WU, CY
- EFFICIENT PHYSICAL TIMING MODELS FOR CMOS AND-OR-INVERTER AND OR-AND-INVERTER GATES AND THEIR APPLICATIONS / WU, CY;SHIAU, MC
- CMOS NONTHRESHOLD LOGIC (NTL) AND CASCODE NONTHRESHOLD LOGIC (CNTL) FOR HIGH-SPEED APPLICATIONS / WANG, JS;WU, CY;TSAI, MK
- EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS / HWANG, JS;WU, CY
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