完整後設資料紀錄
DC 欄位語言
dc.contributor.author劉政宏en_US
dc.contributor.authorCheng-Hung Liuen_US
dc.contributor.author李鎮宜en_US
dc.contributor.authorChen-Yi Leeen_US
dc.date.accessioned2014-12-12T01:34:42Z-
dc.date.available2014-12-12T01:34:42Z-
dc.date.issued2003en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009111591en_US
dc.identifier.urihttp://hdl.handle.net/11536/43546-
dc.description.abstract在此論文中,我們提出以記憶體為基礎的低功率之可變長度解碼器演算法與硬體架構設計,有系統的最佳化流程使的跟原始的可變長度解碼器在有同樣的工作效率時降低了功率消耗。對於實際的多媒體何通訊而言,實現了完全可程式的高效率低功率的解壓縮方案。 此論文首先提出複習之前已經提出可使可變長度解碼有低功率消耗的方法。我們會介紹前綴碼先解法,查閱表格分割法,桶形移位器控制線分割法,可變長度碼偵測器分割法,可變長度碼快取法。利用上述的改進方式,硬接線的可變長度解碼器就可以有非常低的功率消耗。 使用之前已經提出的改進方式,我們將傳統以群組為基礎隻可變長度解碼器改良成兩種低功率的版本。一個稱作連續查表法,另一個稱作平行查表法。連續查表法使用查閱表格分割法,可變長度碼偵測器分割法與可變長度碼快取法。平行查表法只使用查閱表格分割法與可變長度碼快取法。作平行查表法的功率消耗比作連續查表法低且取回代號所需要的時脈週期數也較短。使用這些改信方法,我們就可以成功的作出以群組為基礎之低功率可變長度解碼器。 我們將代號重新排列且使用分組的可變長度碼快取記憶體與分組的全組偵測器,使得多編碼表融合之可變長度解碼器架構有全新的風貌且其可以有比起原始設計的低非常多的功率消耗。因為平行的群組搜尋,低功率的多編碼表融合之可變長度解碼器依然保持高的代號產出率。因此,這個改進的可變長度碼解碼器仍可以達到低功率與高效能的要求。zh_TW
dc.description.abstractIn this dissertation, the algorithm and architecture of low-power memory-based VLC decoder designs are presented. Systematic optimization procedures are proposed to reduce the power consumption and maintain the same operation throughputs as the conventional design. Efficient decompression schemes with full programmability are achieved for real applications in multimedia and communications. This dissertation first presents algorithms used in previous works to decrease power consumption of VLC decoders. VLC detector sizing, barrel shifter control line splitting, prefix pre-decoding, table partitioning and VLC caching are presented. With these improvements, the hard-wired VLC decoder can have low power consumption. Employing techniques previously developed, conventional group-based VLC decoder is adapted into two versions. One uses serial look-up algorithm, and the other uses parallel look-up algorithm. Serial look-up solution uses VLC detector sizing, table partitioning and VLC caching while parallel look-up solution only uses table partitioning and VLC caching. The power consumption performance of parallel look-up architecture is better than serial look-up one as well as the symbol retrieval time. With these low-power algorithms, a low-power group-based VLC decoder is formed. Applying symbol reordering, 2-set VLC caching, 2-way group detector partitioning, multi-table-merged VLC decoder is reborn to have much lower power than conventional one. With parallel group searching, the low-power MTM VLC decoder obtains a high symbol rate. Consequently, this VLC decoder design satisfies the requirements of low power systems and content-adaptive VLC decoder.en_US
dc.language.isoen_USen_US
dc.subject低功率zh_TW
dc.subject可變長度碼zh_TW
dc.subject解碼器zh_TW
dc.subjectLow-poweren_US
dc.subjectVariable Length Codeen_US
dc.subjectDecoderen_US
dc.subjectMemoryen_US
dc.title以記憶體為基礎之低功率可變長度解碼器設計zh_TW
dc.titleLow-Power Memory-Based VLC Decoder Designsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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