多輸入多輸出正交分頻多工系統中頻率域封包欄位偵測與載波頻率偏移估計之實做

Abstract

由於可增進效能與降低正交多頻分工系統上對類比轉數位轉換器的需求，頻率域前端技術變得越來越受人注目。在本篇論文中試著實現兩種頻率域演算法：頻率域上的邊界偵測與頻率域上的載波頻率偏移估算。頻率域上的邊界偵測演算法可在低訊噪比衰退環境中找出正確訊號邊界。為了解決嚴重的衰退與雜訊，使用了最大相似序列估計的重複序列搜尋。根據模擬的結果，在無循環字首直接序列展頻，單輸入單輸出與多輸入多輸出正交多頻分工系統，帶有100 ppm的載波頻率偏移，訊噪比小於或等於6dB，並在多重路徑的環境下，邊界偵測的錯誤率將會小於百分之一。在實現方法上，若頻率域上的邊界偵測演算法使用了0.18微米製程，總共需要二十五萬六千個閘數，供應電壓在1.2伏特下需消耗40.2毫瓦。因此我們可說此演算法不但可以確保得到足夠的效能，而且也可在頻率域正交多頻分工系統架構下同時支援正交多頻分工系統與非正交多頻分工系統。在另一方面，頻率域上的載波頻率偏移估算演算法是基於加上一個虛擬的載波頻率偏移後所得到的載波頻率偏移新演算法，此演算法適用於存在有IQ不平衡效應的情況下並且可以容忍2dB的增益錯誤與20度的相角錯誤在多重路徑的環境中，此演算法只需要三個連續的訓練序列，並加上額外的頻率偏移藉以減少白色高斯雜訊的影響。模擬的結果顯示出偵測誤差小於傳統載波頻率偏移演算法。在實現方法上，若頻率域上的載波頻率偏移估算演算法使用了0.18微米製程，總共需要四萬九千個閘數。

Frequency-domain (FD) front-end is an attractive technology to improve performance and to reduce analog-to-digital (A/D) requirements of orthogonal frequency-division multiplexing (OFDM) modems. This thesis tries to implement two algorithms in frequency domain: boundary detection in FD (FD-BD) and carrier frequency estimation in FD (FD-CFO). The FD-BD searches the symbol boundary in low-SNR fading environments. Am iterative sequence search with maximum likelihood sequence estimation (MLSE) is built to resist severe fading and noise. Simulation of non-cyclic prefix (non-CP) direct sequence spread spectrum (DSSS), single-input single-output (SISO) and multiple-input multiple-output (MIMO) OFDM hint the detection errors with a carrier frequency offset (CFO) of 100 ppm and SNR ≦ 6dB are less than 1% in frequency-selective fading. The FD-BD is implemented via 0.18-μm CMOS library, which require 256K gate count and consumes 40.2mW at 1.2V supply voltage. Hence, FD-BD does not only ensure adequate performance, but also make OFDM and non-OFDM frame synchronizations function in FD-OFDM structures. On the other hand, FD-CFO is a novel CFO estimation algorithm, based on pseudo-CFO (P-CFO), to estimate the CFO value under the condition of I/Q mismatch with 2dB gain error and 20-degree phase error in selective fading channel. The FD-CFO requires three training symbols, and rotates training symbols by adding extra frequency offset to reduce the effects of additive white Gaussian noise (AWGN). Simulation results indicate that the estimation error is lower than Moose’s algorithm and others. The FD-BD is implemented via 0.18-μm CMOS library, which requires 49K gate count.