應用於薄膜電晶體液晶顯示器驅動電路之設計

Abstract

本篇論文的目標是設計應用在液晶顯示器的驅動電路，並且探討能夠達到快速充放電、高解析度、低飄移電壓以及低功率的可能性。液晶顯示器的驅動電路可分為閘級驅動電路和源級驅動電路；閘級驅動電路是由移位暫存器、電位轉換器和輸出緩衝器組成，而源級驅動電路則是由移位暫存器、閂鎖器、電位轉換器、數位對類比轉換器和輸出緩衝器所組成。 要達到快速充放電的目標，我們採用了有快速充放電、超低靜態電流特色的B類緩衝器架構。由於隨著解析度的提升，相對的源級驅動器的輸出緩衝器準確度更顯的重要，因此本論文主要的重點在於設計出一個低飄移電壓的源級驅動器，而為了達到此目標我們運用了chopper offset cancellation技巧，把飄移電壓壓到最小。在高解析度方面，我們實作了一個10位元解析度數位對類比轉換器，架構則是採用Voltage scaling架構，有面積小的優點。 另外在低功率消耗方面，我們設計了電荷共享的電路，half recycling可節省二分之一動態功率，而triple charge recycling可節省三分之二的動態功率。以上電路皆在0.35μm CMOS製程中試製晶片。

In this thesis, we focus on the driver circuits design for TFT-LCD display, and the possibility of high slew-rate, high-resolution, low-offset-voltage, and low power consumption is discussed. The driver circuits of LCD are composed of two parts, the gate driver and the data driver. Gate driver consists of shift registers, level shifters, and output buffers. Data driver is composed of shift register, level shifter, latch, digital to analog converter, and output buffers. In order to achieve high slew-rate performance, a class-B buffer which is capable of high slew-rate and extremely low statistic current has been proposed. As the resolution bits become higher, the accuracy of the output buffer becomes more and more important. In this thesis, chopper offset cancellation techniques to reduce input offset voltage has been achieved. For high resolution, a 10-bit digital to analog converter with voltage scaling architecture and small layout area has been implemented. In addition, charge recycling circuits has been introduced to reduce more power consumption. Half recycling can reduce about 1/2 dynamic power, where Triple charge recycling can reduce about 2/3 dynamic power. All of the above circuits has been designed and fabricated in a 0.35 μm CMOS process.