奈米固相磊晶製作碳化矽應變矽場效電晶體之研究

Abstract

在前瞻超大型積體電路元件中，為了克服金氧半場效電晶體元件微縮的挑戰，許多新穎的應變矽元件結構技術已被廣泛的採用來提升元件效能。其中，最為所了解的應變矽技術為鍺化矽磊晶製程，藉由導入元件中的源極和汲極壓縮應力，P型電晶體元件通道載子移動率的增加亦提升了元件效能。而N型電晶體元件則需導入拉伸應力來增加通道載子移動率，藉由碳化矽其較小的晶格常數磊晶於源極和汲極中以產生較大的拉伸應力，因此新型碳化矽應變矽技術已漸漸獲得關注及應用。 有兩種方法可實現N型電晶體元件上的碳化矽應變矽技術。其一為在元件中的源極和汲極區域先挖出凹槽，然後利用選擇性磊晶製程技術來成長碳化矽磊晶。其二為較新方法，以碳分子植入技術及固相磊晶(solid phase epitaxy ; SPE)熱回火來完成碳化矽磊晶結構。雖然，碳化矽藉由固相磊晶製程所產生之碳原子濃度較選擇性磊晶製程為少，但是碳化矽固相磊晶製程為較簡易製程且低製造成本技術，並可被整合入超大型積體電路元件製程。 然而，電晶體元件中的源極及汲極電阻和擴散電阻將因碳化矽固相磊晶製程的導入而增加，如此將使得於應變矽技術中所獲得的效益減損。此外，來自於其它後續半導體製程所產生的熱預算亦將引起碳原子的析出效應，如此將進一步減少碳原子濃度並減少元件通道所受到的應力。因此，研究適當的碳分子植入時機與固相磊晶熱回火的交互作用為重要議題，尤其當整合碳化矽固相磊晶製程於具有多重高溫熱回火(RTP和LSA)的先進的奈米半導體技術。現今，碳化矽固相磊晶製程以其相容於先進的高介電係數介電層暨金屬閘極(HKMG)於閘後整合元件技術(RMG)並導入較多的應變矽效應而引起更多的討論。 本論文中，我們首先著眼於利用控檔晶片進行碳分子佈植及回火熱效應的研究以期得到最佳化的製程組合，而最主要的評鑑指標為碳原子於晶格替代點(substitutional)濃度及其等效電阻值，藉由X光繞射儀(X-ray Diffractomety ; XRD) 及四點探針(4-point probe)可分別取得上述資訊，然後將此一最佳碳化矽固相磊晶製程條件應用於先進N型電晶體元件製造。45奈米節點技術電晶體元件驗證了碳化矽固相磊晶製程對元件效能的改良，然而，28奈米節點技術電晶體元件採用了更新的碳化矽固相磊晶製程觀念，卻因碳分子佈植散射效應而僅得到相近的元件效能。廣泛的碳化矽固相磊晶應變矽N型電晶體特性分析，例如: 載子移動率、元件環境效應、元件不匹配性、可靠度等都涵蓋於討論中，由本文的研究我們歸納出最佳的碳化矽固相磊晶製程以供應用，來達成對先進元件效能增益的需求。

In order to overcome the scaling challenge faced by MOSFETs in VLSI, the various strained-Si technologies have been adopted as essential components for devices performance boost. The most well known strained-Si technology is the embedded SiGe (eSiGe) epitaxy process with compressive stressors, which is introduced into the S/D area to enhance the PMOS performance. And, NMOS favors tensile stressors, the embedded SiC (eSiC) S/D stressors have gained many interests due to the large tensile stress resulting from the smaller lattice constant of SiC. There are two different approaches to realize the eSiC S/D for NMOS. One is to recess S/D region and grow SiC using selective epitaxy process. Another one is reported recently to use Carbon ion implantation (I/I) and solid phase epitaxy (SPE) thermal anneal to form SiC in the S/D. Although the carbon concentration ([C]sub) caused by SiC SPE process is lower than that by the selective epitaxy process, the Carbon I/I and SPE approach is much easier with lower cost to be integrated into full CMOS process. However, both the increased S/D and extension sheet resistance (Rs) caused by introduction of SiC SPE process will degrade the performance gain obtained from the strain effect. Moreover, the thermal budget from subsequent processes could induce carbon atom precipitation out from substitutional sites and reduce the stress in the channel. Hence it is important to have an insight into the right time of Carbon dopant introduction and the possible thermal interactions as high temperature rapid thermal processes (RTP) or mili-second anneal (such as the laser anneal, LSA) is employed in nanoscale technology. Nowadays, the SiC SPE process has attracted much attention because the technology is compatible with the replaced metal gate (RMG)/high-K scheme for the advanced CMOS technology. In the thesis, first, we focused on finding the optimized process scheme with blanket wafers by varying the Carbon implant condition and studying the effect of thermal annealing. The major indexes were the substitutional carbon concentration (via XRD extraction) and the sheet resistance (via 4-point probe). Afterwards, we applied the suggested SiC SPE schemes for the advanced NMOS devices fabrication. The device of 45nm technology node did show performance boost. However, the device of 28nm technology node with further optimization encountered carbon scattering issue and only depicted comparable performance with that without SiC SPE process. The other comprehensive analyses such as mobility, proximity effect, devices mismatch and reliability …etc were also investigated. As a result, we reported an optimized SiC SPE process scheme for the advanced technology applications.