直序式超寬頻無線射頻接收機之CMOS帶陷可調式低雜訊放大器設計與研究

Abstract

本篇論文主要是探討帶陷式低雜訊放大器在直序式超寬頻(DS-UWB)之設計與應用。電路的設計主要是藉由實驗室內的完成電路 (Notch LNA)，加上壓控電容，在UWB 的頻帶內達到頻率可調的效果。 在超寬頻(Ultra Wide Band) 的工作頻帶(3.1 ~ 10.6GHz)內,除了DS-UWB 的訊號外,尚有IEEE 802.11a 的WLAN 信號存在於5~6GHz 的頻帶內，這些訊號的存在會與DS-UWB 的訊號產生交互調變失真(Inter-modulation distortion)，進而干擾到DS-UWB 的訊號。因此，直序式超寬頻調變技術在定義其工作頻帶時，刻意避開了5~6G 的頻帶，達到降低信號干擾的目地。 電路架構上是先以兩個電感所形成的Transformer feedback，做第一級的輸入匹配，達到寬頻匹配與雜訊抑制的效果，再於第一級的放大器後方加上一可調式帶陷濾波器，用來衰減干擾訊號(5~6GHz)，接著再串一級放大器來提高增益。當中，為了降低功率損耗，每一級的放大器都只用單一電晶體去完成，而非Cascode 的架構，因而，此電路的直流偏壓只需要一伏特。最後，將LNA 串接 源極隨耦器(source follower)完成寬頻輸出阻抗匹配。 此寬頻低雜訊放大器模擬結果如下：頻寬為3 ~ 10 GHz，平均增益為11dB，雜訊指數為2 ~ 4 dB，輸入反射係數小於10 dB，input P1dB 最小值為-24dBm，IIP3最小值為-5dBm，功率消耗為16.8 mW

This thesis discusses the design and analysis of a band notch low-noise amplifier applied in the receiver of DS-UWB. The design in this thesis is based on a finished circuit “Notch LNA” and then makes it tunable in virtue of the adding varactor. The signal within the operation band of UWB (3.1 ~ 10.6GHz), includes not only the signal of DS-UWB but the WLAN signal of IEEE 802.11a (5~ 6GHz). These undesired signals will cause inter-modulation and hence interfere with the signal of DS-UWB. Thus, the operation band of DS-UWB doesn’t include 5~6 GHz to prevent interference.About circuit architecture in this thesis, transformer feedback is the first stage for getting broadband input matching and low noise contribution. Tunable notch filter is inserted in back of the first transistor, and then cascade another transistor to increase gain. For getting lower power consumption, we use single transistor in each stage so the applied voltage of amplifiers just 1 volt only. Finally, this LNA series with a source follower for output matching. The simulation results are as follows: The bandwidth is 3 ~ 10 GHz. The average gain is 12 dB. The noise figure is 2 ~ 4 dB. The input return loss is lower than 10dB.The input P1dB(min.) is -24dBm. The IIP3(min.) is -5dBm. The power consumption is 16.8 mW.