1.8V、10位元、每秒100百萬次取樣CMOS導管式類比數位轉換器

Abstract

隨著製程技術的進步，超大型積體電路系統可以用更小的晶片面積達到更高的運算速度。在現行的通訊系統中，訊號將先透過一個類比數位轉換器將接收到的類比訊號量化，以供後級的數位電路執行更複雜的訊號處理；為提昇整體系統之性能，類比數位轉換器往往和龐大的數位訊號處理系統整合在單一顆晶片上。 伴隨著電晶體尺寸的縮小，系統晶片的供應電壓也隨之下降。因此，低電壓類比數位轉換器將伴演愈形重要的角色。

本論文中的主要目標為設計一個操作在1.8V DC之下、10位元、每秒100百萬次取樣導管式類比數位轉換器。其採用每級1.5-bit解析度的架構，以提高整體類比數位轉換器的運算速度。同時結合數位校正技術以增加比較器的偏移電壓容忍度，而不須要前級預先放大器，進而節省功率的耗費。在取樣並保持電路的設計上，其採用翻轉迴授(Flip-Around)架構，使得電路在保持模式時可具有最大的回授因子，減小運算放大器所須的頻寬需求及功率消耗；此外，為了因應低電源電壓的操作，本設計利用升壓技術(bootstrapping technique)以控制前級取樣開關，進而減低因低電壓操作時對取樣保持電路線性度的影響。

整個類比數位轉換器原型晶片以TSMC 0.18μm CMOS製程製作，晶片面積為3.2mm2；當輸入為2.0Vpp的差動訊號且在100MHz的轉換速度(conversion rate)之下，此類比數位轉換器達到65dB訊號雜訊動態範圍(SNDR)，微分型非線性誤差(DNL)和積分型非線性誤差(INL)皆小於0.2LSB，其電源供應為1.8V的單電壓，功率消耗為88mW。

The rapid developments of IC technology have made it possible to realize a VLSI system chip with higher operating speed in a smaller feature size. In a modern communication system, input signal is quantized by an analog-to-digital data converter for the following complicated signal-processing in the digital domain. In the current IC design trend, analog to digital data converters and the sophisticated digital circuits are integrated on a single chip for higher performance. As the operating voltage is scaled down along with the shrinkage of device size, a low voltage ADC is demanding and would play an important role in the future.

The objective goal of this thesis is to realize an 1.8 V, 10-bit, 100MS/s pipelined analog to digital data converter. An 1.5-bit/stage architecture is adopted for higher operating speed. Cooperating with digital error correcting technique, it tolerates higher comparator’s input offset voltage and no preamplifier is needed, thus lowers the total power dissipation. In addition, a flip-around sample and hold architecture in the front-stage is utilized for a maximum feedback factor, so as to relax OP’s gain-bandwidth requirement and reduce power dissipation. Furthermore, to operate under a supply voltage as low as 1.8 V, voltage bootstrapping technique is adopted for controlling the switches in the front-stage. It can reduce the impacts of linearity degradation due to the limitation of low supply voltage.

The ADC prototype is fabricated in TSMC 0.18μm CMOS process, and it occupies an chip area of 3.2mm2. With an 2.0Vpp differential input signal, the analog-to-digital converter manifests a SNDR up to 65dB at 100 MHz conversion rate. The DNL and INL are both less than 0.2LSB. Operating under a 1.8V supply, total power consumption is 88mW.