新穎環繞式閘極複晶矽奈米線於薄膜電晶體非揮發性記憶體之特性分析

Abstract

本文主軸探討新穎環繞式閘極複晶矽奈米線應用薄膜電晶體非揮發性記憶體之特性。藉由現今天廣泛研究的具氮化矽儲存層快閃記憶體結構為根基，整合多通道奈米線及環繞式閘極的優點，使非揮發性的記憶體特性更加向上推升，同時具有更降低成本、更節省能源的優點，使元件更具吸引人的優勢。此外，為了要克服提高效能對於元件可靠度所帶來的負面效應，必須藉由雙重閘極以及儲存層埋藏奈米點的方式，利用其物理優勢以解決可靠度問題，未來可以是具有相當潛力的元件。

本論文克服製程技術上的問題，提出新穎的具備雙重閘極及埋藏奈米點的結構之環繞式閘極複晶矽奈米線之薄膜電晶體非揮發性電晶體的元件以供分析。利用多種既有的分析系統來作論述，從掃描式電子顯微鏡及穿隧式電子顯微鏡的影像來證明立體平面結構的正確性，此外也藉由電性討論來取得元件的效能及可靠度相關結果，利用物理解釋得出完整的結論，可以讓討論的合理性更趨於完善。

The novel gate-all-around thin-film transistor non-volatile memory devices are introduced. The thin-film transistor non-volatile memory has been widely investigated, especially in silicon/oxide/nitride/oxide/silicon (SONOS) structure, since there is a plenty of advantages such as low cost and high density array. To integrate gate-all-around structure to these devices is good idea to improve performance of non-volatile memory. In this work, the multi-channel nanowires-based gate-all-around thin-film transistor non-volatile memories have been fabricated successfully. The characteristics of thin-film transistors can be enhanced by multi-channel structure; moreover, gate-all-around structure also aid performance increasing. On the other hand, both dual gate structure and nanocrystal formation are also integrated to these devices, and the reliability can be improved significantly. For the future, this novel structure has much potential application.

In this thesis, various analyses are provided to demonstrate some better properties in these devices. The structure of devices is confirmed by scanning electron microscopy and transmission electron microscopy images. Furthermore, high performance and reliability are exhibited by electrical and physical analysis.