奈米金氧半電晶體佈局對高頻特性與雜訊之影響以及低功耗超寬頻低雜訊放大器之設計應用

Abstract

本論文主要著重於奈米金氧半電晶體佈局相關性之高頻特性及高頻雜訊，探討的製程為65奈米及45奈米製程技術。最終之目的是為低功耗，寬頻寬且低雜訊的射頻電路設計決定出有用的方針。論文中有興趣的雜訊種類主要是射頻及類比電路設計相關，包含低頻率頻段之隨機電報雜訊(RTN)和高頻率頻段之熱雜訊。關於隨機電報雜訊之研究，使用伴隨足夠小面積之45奈米SiC施壓n型金氧半電晶體，且提出一個二階阱模型以合理解釋實驗數據。至於高頻雜訊，基於散射參數及雜訊量測考量，設計複閘極金氧半電晶體射頻測試結構，同時此結構也適用為了得到元件高頻特性所於之de-embedding結構。佈局相關效應，如STI壓迫導致之ueff變化，TCR導致之dW，閘極電阻(Rg)變化，和寄生閘極電容皆由各種電性特徵來作探究。上述所提到的元件參數效應作延伸討論其對高頻元件特性的影響，如fT和fMAX，以及在低頻率頻段和高頻率頻段之雜訊參數。對寬頻寬，低功耗，低雜訊之射頻電路設計而言，瞭解佈局相關的作用可作為佈局效應最作化之引導。最後，佈局引導之複閘極數金氧半電晶體設計被應用於設計一個低功耗，超寬頻(UWB)低雜訊放大器。65奈米製程中，fT和fmax大於100GHz的複閘極n型金氧半電晶體研究使得放大器設計上得到益處，且此放大器應用順向基極偏壓方案以協在可接受的增益和雜訊下，實現低偏壓電壓及低功耗設計。

This thesis is focusing on the layout dependence of high frequency characteristics and noise in nanoscale MOSFETs using 65 nm and 45 nm CMOS technologies. The ultimate goal is a useful guideline for low power, broadband, and low noise RF circuit design. The noises of major interest in this thesis, for RF and analog circuits design involve random telegraph noise (RTN) at lower frequencies and thermal noise at higher frequencies. An investigation on RTN was performed on 45 nm SiC strained nMOS with sufficiently small area and two level trapping model was proposed to fit the experimental. As for high frequency noise, multi-finger MOSFETs were designed in RF test structure for S-parameters and noise parameters measurement, and required deembedding for high frequency characterization. Layout dependent effects such as STI stress introduced □eff variation, TCR induced □W, gate resistances (Rg), and parasitic gate capacitances have been explored through an extensive characterization. The mentioned effects on device parameters have extended impact on high frequency performance parameters like fT and fMAX, and noise parameters in both low frequency and high frequency domains. The understanding of layout dependent mechanisms can guide layout optimization in RF circuit design for wideband, low power, and low noise. To the end, the layout guideline of multi-finger MOSFETs was applied to the design of a low power ultra-wide band (UWB) low noise amplifier (LNA). The super-100 GHz fT and fMAX offered by 65 nm CMOS technology to multi-finger nMOS can benefit UWB design and the implementation of forward body biases scheme can help realize low voltage and low power design with acceptable gain and noise.