IEEE 802.15.3c 之同步偵測的設計與實作

Abstract

在本論文中呈現了適用於IEEE 802.15.3c的標準規格中之單一載波(SC)和多重載波(HSI)兩種模式的前置碼(preamble)/符號邊界與載波頻率飄移的同步估測。基於利用前置碼結構之相關性(correlation)的演算法，我們提出了一個有效率的單一架構及循序的偵測機制來實現同步偵測。為了達到高速取樣頻率的需求，整體基頻電路使用八倍平行化並且操作於333 MHz的工作頻率。在未具有編碼保護下，SC和HSI兩種模式各別在信號雜訊比為12 dB時，可以達到8.92×10-4和1.43×10-2的位元錯誤率。我們所提出的同步偵測架構以65奈米1P9M CMOS製程實作，一共使用了19.9萬個邏輯閘數量(gate count)及平均60.16毫瓦的功率消耗，其中包括63.26 %的記憶體元件是與系統中之適應性頻率域通道等化器(FDE)共用。此外，應用低功耗的技術節省了42.5 %的功率消耗。

In this thesis, a jointed preamble/boundary detection and fractional CFO estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and a single hardware for dual SC/HSI modes and three detection operations. In order to achieve the requirement of sampling frequency, the baseband design is 8x parallelism and is operating at 333 MHz clock rate. The achieved bit error rate (uncoded) at 12 dB SNR for SC and HSI modes are 8.92×10-4 and 1.43×10-2, respectively. The proposed architecture of synchronization detection is implemented using 65 nm 1P9M CMOS process and the total gate count is 189k with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer. Moreover, the power consumption is saved 42.5 % by applying low power techniques.