適用於高速移動之無線都會網路空時區塊碼正交分頻多工干擾消除器設計

Abstract

近年來，時空區塊碼(space-time block code; STBC)已被證實可以提供高編碼率及好的效能。在多根傳輸天限的正交多頻分工（orthogonal frequency-division multiplexing; OFDM）的系統應用中，時空區塊碼可增加分集增益(diversity gain)而且也被IEEE802.16e/m規格支援。但是時空區塊碼對於單一編碼字元時間間隔內的通道時域變化非常敏感，這些變化將使得單一邊碼字元內的符元資料互相干擾；而且時變性多路徑通道也會在正交多頻分工系統的次載波間引發正交多頻分工次載波間干擾(Inter-carrier Interference;ICI)效應。這些干擾雜訊會破壞空時區塊碼與正交分頻多工系統結合之系統應用（STBC-OFDM systems）的性能，因此我們必須一種空時區塊碼正交分頻多工干擾消除器才能在無法取得詳細的通道狀態資訊（channel state information; CSI）的狀況下達到更好的效能。 這篇論文將提出一個可適用於高速移動環境中兩根傳送天線與一根接收天線之空時區塊碼與正交分頻多工系統結合之系統的干擾消除器。此空時區塊碼正交分頻多工干擾消除器的設計是基於一套現存IEEE802.16e規格的接收器，但是它也可以輕易的修改為IEEE802.16e規格。設計的目標是在高達時速360公里的移動環境中提供效能的改善，我們將提出的設計與一套被研究過的兩階段通道估測器(two-stage channel estimator)搭配來展示效能，在時速240及360公里、訊噪比(signal to noise ratio;SNR)高於15dB、16正交振幅調變（16 quadrature amplitude modulation; 16-QAM）的環境中可減少位元錯誤率（bit error rate; BER）超過2倍。我們以90 nm CMOS製程實現此干擾消除器設計。總共需要42,277個邏輯閘，在78.4MHz的操作頻率與1 V工作電壓下，其功率消耗為1.45 mW。干擾消除器設計中大約61%的邏輯閘可以與現有的兩階段通道估測器共用，額外的負擔只占原先兩階段通道估測器的4.9%。

In recent years, space time block code (STBC) has been shown to give high code rate and good performance. It is suggested to be applied in an orthogonal frequency division multiplex (OFDM) system since OFDM system with multiple antennas can provide better communication performance by exploiting transmit diversity and it was also supported by IEEE 802.16e/m standard. Nevertheless, STBC is sensitive to the temporal channel variation inside one code word which results in the symbols inside one codeword interferes with each other. Also, time-varying multipath channel introduces intercarrier interference (ICI) among OFDM subcarriers. These interference noises degrade STBC-OFDM system performance. Hence, an STBC interference cancellation scheme is required for better performance when the detailed channel statistics information (CSI) variation is unavailable. This thesis proposes an STBC interference canceller for any STBC-OFDM systems with two transmit antenna and one receive antenna in mobile environment. The proposed STBC interference canceller is applied in an existed IEEE802.16e STBC-OFDM receiver and can easily be adapted into IEEE802.16m STBC-OFDM receiver, too. The proposed design aims to provide performance improvement under the vehicle speed up to 360 km/hr. The performances have been demonstrated through the simulation of the proposed design with a previously proposed two-stage channel estimator. At vehicle speed of 240 and 360 km/hr and signal to noise ratio (SNR) over 15dB for 16 quadrature amplitude modulation (16QAM), the proposed design can provide more than 2 times bit error rate (BER) improvement. The proposed design is implemented in 90 nm CMOS technology. The gate count is 42,277 and the power dissipation is 1.45 mW at 78.4 MHz operation frequency from a supply voltage 1V. About 61% gates of our proposed STBC interference canceller are shared with the existed two-stage channel estimator design, and the overhead is only 4.9%.