應用於第三代PCI Express之高速串列發射機設計

Abstract

現今科技日新月異，電腦通訊十分發達，傳送資料量也越來越多。過去於電腦內部的通訊是採用平行匯流排傳輸，雖然多加排線即可提升傳輸的資料量，但是晶片越做越小，而成為提升速度上的瓶頸。串列連結技術正解決了平行匯流排的問題，但資料經過通道上的 高頻損耗也相對來的嚴重，造成接收端無法正確接收。 本論文是設計應用於電腦晶片間連結的第三代PCI Express之高速串列發射機電路，我們會介紹幾個多工器與去強化器的架構，並且考量優缺點來實現。其模擬結果符合PCI Express的規格，由眼圖來看，顯示去強化可減輕接收端等化器設計的困難，並且設計 簡易及低功耗。 全晶片是以UMC 55nm互補式金氧半導體製程技術來製作，其總共的面積為0.71mm2。

The rapid developments of IC technologies have enabled varieties of computer communications. In the past, data communication inside computer system is based on parallel buses. Although its bandwidth can be enhanced by increasing channel numbers. As is limited by chip area and form factor, it becomes the bottleneck in terms of speed. This problem can be circumvented by replacing parallel buses with high speed serial I/O. But the channel loss at high frequency becomes severe and may cause the receiver fail to work properly. This thesis describes the design of high speed transmitter for PCI Express Generation III. Several multiplexer and de-emphasis architectures are investigated to evaluate their advantages and disadvantages. The chip performance can meet the specifications of PCIe 3.0 by simulation. By de-emphasis technique at transmitter side, it relaxes design complexity, and reduces power consumption at the receiver. The experimental prototype is implemented in 55nm UMC technology. Chip area is 0.71mm2.