應用在系統封裝內的鈦酸鍶鋇電容之電性與熱穩定改善與鋁/HSQ和銅/HSQ之導線系統的高頻特性研究

Abstract

隨著半導體技術的發展，可以利用系統封裝的方式整合感測器、記憶體模組與邏輯元件等，使得多功能的可攜式電子產品變得不是遙不可及的夢想。而系統封裝的方法也可以大幅降低成本，也可以減少研發產品上市的時間。而電容卻是系統封裝內不可缺少的元件，因為它可以應用在動態隨機存取記憶體、微波電路，類比電路等。但是在元件不斷的微小化過程，仍須提升電容密度，所以在未來的製程發展中，將會利用高介電常數材料作為電容之介電層。 而本論文研究的利用鈦酸鍶鋇/鉻/鈦酸鍶鋇結構作為電容的介電層，這是因為鈦酸鍶鋇本身擁有非常高的介電常數。當在上下層鈦酸鍶鋇的中間穿插一層奈米厚度的鉻層，可以改善鈦酸鍶鋇電容的電性與熱穩定性。雖然鈦酸鍶鋇/鉻/鈦酸鍶鋇三層結構會降低介電常數，但它卻也降低損耗因素，降低表面粗糙度。也可以降低電容的溫度係數，提升熱穩定性。這對於內埋電容的特性有很大的助益，因為元件的操作往往會使的整個系統溫度上升，所以電容值保持熱穩定是一件重要的課題。根據本論文的分析可以得到，在穿插一層奈米厚度的鉻層後，在氧氣氣氛下作800oC退火，上層的鈦酸鍶鋇表面會析出二氧化鈦的奈米顆粒或薄膜，由於二氧化鈦的介電常數對於溫度改變而言相對是穩定，並且是正相關，鈦酸鍶鋇的溫度係數是負數，所以適當厚度的二氧化鈦可以提高鈦酸鍶鋇/鉻/鈦酸鍶鋇結構電容的熱穩定性。本論文也針對奈米鉻層的厚度對於鈦酸鍶鋇的平行板電容的特性影響作討論。 另一方面，製程不斷微縮，傳遞快速和完整的訊號至電容或其他元件變得更加困難，這是由於整個系統在傳輸快速或高頻的訊號時，導線寄生效應會隨著製程密度的增加而更為嚴重。解決的方式就是降低導線之間的絕緣電容值，這可以降低訊號傳輸的延遲、雜音干擾、功率損耗。本論文也利用HSQ作為低介電常數材料分別搭配銅導線與鋁導線，所以本研究針對高頻訊號傳遞效率、電容值、擴散阻絕層和可靠度作製程最佳化的探討研究。最後，利用本研究最佳化的HSQ材料的導線技術，與最佳化的電容(鈦酸鍶鋇/鉻/鈦酸鍶鋇)整合進入系統封裝技術。我們以模擬計算得到，高頻訊號沿著導線傳遞電容的特性，發現高頻訊號傳遞時，整個系統仍保持極佳的熱穩定性與電性。所以本研究的電容(鈦酸鍶鋇/鉻/鈦酸鍶鋇)是非常適合應用在未來的可攜式通訊電子產品中。

Recently, the technology progress provides the major opportunities in both miniaturization and integration for advanced and portable electronic products, leading the community to believe that someday 3-D packaging approaches will come true, referred to as system-on-package (SoP). Some existing and emerging applications including sensors, memory modules and embedded processors will incorporate into the SoP approach and offer solutions towards faster time-to-market and business impediments. During the integration and minimization technology, the capacitance density in the dynamic random access memory (DRAM), radio frequency (RF) circuit, and analog circuit continues to increases. Therefore, the high k dielectrics are used. Integrated into SoP, high k dielectric must meet many challenges of integration. The dielectric of Ba0.7Sr0.3TiO3/Cr/Ba0.7Sr0.3TiO3 (BST/Cr/BST) was developed for the capacitor of SoP application. With the insertion of a Cr interlayer, the temperature coefficient of capacitance (TCC) of specimens with BST/Cr(2nm)/BST multifilm dielectrics could achieve the improvement compared with that of BST monolayer, and the dissipation factor of the BST/Cr(2nm)/BST structure could also be reduced. The dielectric constant of BST/Cr(2nm)/BST structure decreases, but its dielectric constant of 371 is still very high. On the other hand, based on the International Technology Roadmap for Semiconductors (ITRS), total power consumption continues to increase. The chip heat dissipation and thermal stability for the device become the serious challenges for the SoP applications. BST/Cr(2nm)/BST shows the good TCC, while it is helpful to integrate into SoP. In order to transfer the integral signal to the embedded capacitor in SoP system, the interconnect must provide high-speed and low-loss signals. However, the parasitic effects associated with interconnect become severe and cannot be ignored when the operating frequency increases. Small parasitic capacitances (C) between interconnects are required to reduce the crosstalk, power consumption, and RC delay associated with the metal interconnect system. Therefore, interconnect with low k property were required. In this study, hydrogen silsesquioxane (HSQ) thin films prepared, and the high frequency characteristics of Al/HSQ system and Cu/Ta/HSQ system are investigated and compared with those of Al/SiO2 system. The optimal interconnect case will be indicated in this thesis. Finally, according to the optimal conditions of the capacitor and interconnect in this thesis, we can simulate the high frequency signal to transmit to the capacitor of BST/Cr/BST through HSQ/interconnect. The result indicates it is quite capacitive below 3GHz even if the temperature and/or applied voltage increase. Therefore, they are very potential to integrate into the SoP application of the portable and the communication.