具猜測能力之高效能算術單元的設計和實現

Abstract

隨著需要大量運算的多媒體和通訊應用的需求增高，電路內的算術單元必須在高頻下工作。因此，如何增進算術單元的效能，使設計能夠操作在高速高頻的運算環境下，已經是目前電路設計考量的重點。 具猜測能力的算術單元設計是先降低關鍵路徑的計算長度，這將導致計算錯誤，因此，此設計再利用數學分析推測的補償值來降低錯誤發生率，來提高整體效能。我們將算術單元切分成兩個小模組，縮短原先算術單元的關鍵路徑的延遲時間，並將這些小模組同時並行運算，以利於增進算術單元的效能。然而這種方式會造成算術單元的運算錯誤，由於計算時間縮減，一些計算無法按時完成計算，導致最後的運算結果錯誤。根據可變延遲設計的概念：加速常用的情況。當常用的情況發生時，我們只需要一個週期來計算；相反的，當最壞的情況發生時，我們需要額外多一個周期，以恢復計算錯誤。因此，我們提出了可變延遲的設計，是利用投機的方法和錯誤恢復的機制來實現。除此之外，更進一步提出了進位估計的技術，應用在可變延遲設計上，以增加在第一個周期的算術單元的計算精確度。 本論文分析了算術單元的關鍵路徑的延遲時間，並依據此分析將算術單元切分成兩個小模組，更進一步分析所提出的進位估計的方式。藉由勘探效能成本函數的方式，我們可以找到最優化的(高效能的)設計參數，這是週期時間和計算精確度之間的權衡。週期時間是指在電路設計中的關鍵路徑所需要的嚴格時序，縮短周期時間可以提高整體設計的效能。計算精確度意味著有多少筆運算可以在一個週期內完成；其餘的情況下，需要額外多一個周期，以恢復計算錯誤，這將會造成效能的退化。根據這些分析，我們實現了高效能的可變延遲設計算術單元。 在我們的模擬，我們採用了多媒體應用：人臉物件偵測和離散餘弦轉換，來證明我們所提出的可變延遲設計算術單元的效能改進。與傳統的設計方法和其他現有的研究相比，所提出的設計可以提高20.9%~21.9%的效能比。而與管線(Pipeline) 設計相比較，在同樣的合成時序(synthesis timing constraint)下，當資料危障發生時，我們的設計的效能比管線設計的效能高47.42%，意味著可以比管線設計快47.42%。在相同的效能下，我們的設計可以比管線設計減少4.20%的面積和24.02%的功率損耗。

With the growing computation-intensive requirement for multimedia and communication applications, the functional units need to work under high clock frequency. Therefore, how to improve the performance of the functional units to enable the design operating in the high-speed and high-performance computing has become the major issue in the current circuit design. The speculating design reduces the computing length of the critical path and this will cause computing error; therefore, the compensating value is speculated by the mathematical analysis to reduce the error probability. We divided the functional unit into two parts and computed them in parallel for reducing the critical path delay and increasing the performance. However, this method will induce the functional unit computing error owing to some computations which are unable to finish computing on time. The concept of variable-latency design is to fast the common case. And when these cases occurring, we only need one cycle to compute; in contrast, when the worst cases occurring, we need another cycle to recover the computing error and this will causing the degenerated performance. Therefore, we propose the variable-latency design which is realized by the speculating method and error recovery mechanism. Furthermore, the technologies of carry estimation are applied to increasing the computing accuracy in the first cycle of the functional units. This thesis analyzed the partition of the function units and the proposed method of carry estimation. By the cost function of performance exploration, we can find the most optimal (high-performance) design parameters which is the trade-off between clock cycle time and the accuracy. In here, the clock cycle time means the tightest timing of critical path need in the design. To shorten the cycle time can improve the performance in design. The accuracy means those cases can be finished in one cycle. The rest of the cases need additional cycles to recover the result and this will degenerate the performance. According to these analyses, the high-performance and variable-latency functional unit is implemented. In our simulations, we adapted several multi-media applications: the object of the human faces detection and the discrete cosine transform (DCT) to demonstrate the improved ratio of the performance in our proposed design. As compared with conventional design methodology and other currently available researches, the proposed design can improve 20.9% ~ 21.9% of performance ratio. The speed in our design can run 47.42% faster than the pipeline design under the same synthesis timing constraint when data hazard occurred. When compare with the pipeline design under the same performance, the area in our design can be reduced 4.20% and the power consumption can be reduced 24.02%.