適用於多模具備平坦雜訊表現之寬頻低雜訊放大器設計

Abstract

本論文針對多模組應用提出使用主動輸入匹配具有平坦雜訊表現之寬頻互補式金氧半(CMOS)低雜訊放大器之設計。本文提出之多級式低雜訊放大器(LNA)包含互補式放大器與共射級放大器架構，並採用主動輸入匹配方法，以達成平坦雜訊和超寬頻之設計目標。在1.8伏的電源供應下消耗17.1毫瓦可達到22.2dB的最大功率增益。可量測到2.85dB的最低雜訊值且在0.6到4G頻寬內平坦雜訊值在2.92dB具有正負0.07dB的變異量。在此提出應用於寬頻之平坦雜訊放大器並經由台積電0.18-μm CMOS 製程進行電路實作，量測出整體具有0.6-6GHz的寬闖頻寬，並且驗證此多級式低雜訊放大器適合應用於多模組系統。運用HFSS建立互補式金氧半(CMOS)微機電(MEMS)電感的3D模型，與模擬其特性並實現與量測此電感來驗證3D模型的可信度。在此論文透過所提出的具有平坦雜訊之放大器與雜訊抑制之放大器來討論高特性品質的互補式金氧半(CMOS)微機電(MEMS)電感的影響。

A flatness noise design of a wideband low noise amplifier for multi-band applications using the active input matching is proposed in this thesis. To achieve flatness noise figure and wide operating bandwidth, the proposed multi-stage LNA employing input active matching technique consists of a complementary common source stage and a cascode common-source stages. The maximum forward power gain (S21) of 22.2dB can be achieved while drawing 17.1 mW from a 1.8-V supply. A noise figure as low as 2.85 dB and 2.92dB flat noise figure with ±0.07dB variation from 0.6-4GHz have been measured. Design optimization for the flat noise figure amplifiers in wide bandwidth applications is also presented and circuit implementation in tsmc 0.18-μm CMOS process shows a 0.6-6GHz bandwidth. The novel topology of multi-stage LNA is applied for the multi-band applications. The proposed low noise amplifier was verified by a RF/Baseband co-simulation. CMOS MEMS inductors are also imported into the proposed low noise amplifier and an amplifier with noise cancellation. 3D model of the CMOS MEMS inductors has been developed and simulated by HFSS and the test-key inductors have been measured to verify the reliability of HFSS 3D model. In this work, the effect of high quality factor of CMOS MEMS inductors will be discussed for the proposed low noise amplifier and an amplifier with noise cancellation.