為取得面積與延遲間較佳平衡之三維可程式邏輯閘陣列架構探索

Abstract

三維積體電路(three-dimensional integrated circuits)在單一晶片(chip)內堆疊多個晶粒(die)，並利用直通矽穿孔(through-silicon vias, TSVs)做為垂直方式的連接，這樣的製造技術被認為是實現更好的系統性能及易於整合的可靠解決方案。標準的二維可程式邏輯閘陣列(2D FPGAs)也可使用同樣的方式，將訊號切換模式從二維的架構拓展至三維，而構成三維可程式邏輯閘陣列(3D FPGAs)架構。主要的作法是將原本二維的切換箱(switch boxes, SBs)取代成「加入直通矽穿孔以提供垂直通道」的三維切換箱。然而，將所有二維的切換箱都取代成充分垂直連接(full vertical connectivity)的三維切換箱會相當耗面積而且非常浪費資源。原因是直通矽穿孔的使用率其實相當低。因此，藉由適當調整三維切換箱的排列方式以及其內部直通矽穿孔的連接數目，可以犧性極少量時間延遲而大幅度的減少所佔面積。在本篇論文當中，我們針對三維可程式邏輯閘陣列提供了一個完整的架構探索。我們提出了許多省面積的新架構，並針對同一架構內不同的直通矽穿孔擺放方式做一個完整評估，目的是為了找出在不同架構內面積與時間延遲間更具平衡的擺放方式。最後，我們提出了數個值得推薦的新架構，可在幾乎沒有時間延遲增加下節省面積達52%。

The emerging 3D technology, which stacks multiple dies within a single chip and utilizes through-silicon vias (TSVs) as vertical connections, is considered a promising solution for achieving better performance and easy integration. Similarly, a generic 2D FPGA architecture can evolve into a 3D one by extending its signal switching scheme from 2D to 3D. That is, replacing the 2D switch boxes (SBs) with the 3D-SBs which add to TSVs for vertical links between different layers. However, replacing all 2D-SBs by 3D ones with full vertical connectivity is found both area-consuming and resource-squandering because the overall utilization of TSVs is extremely low. Therefore, it is possible to greatly reduce the footprint with only minor delay increase by properly tailoring the structure and deployment strategy of 3D-SBs. In this thesis, we perform a comprehensive architectural exploration of 3D FPGAs. Various architectural alternatives are proposed and then evaluated thoroughly to pick out the most appropriate ones with a better balance between area and delay. Finally, we recommend several configurations for generic 3D FPGA architectures, which can save up to 52% area with virtually no delay penalty.