適用於三維積體電路之線性規劃

Abstract

隨著技術的發展，3D IC漸漸成為一種趨勢，但因為是一種新穎的科技，更需要新的EDA技術，而電路分割就是重要的項目其中之一。本篇論文注重在從結構層級去做電路分割，以最 大限度地發揮其效益。首先，我們使用了邏輯運算去解決三維積體電路分割的問題，並轉換成ILP的方程式。我們的ILP方程式可減少TSV的數量和功耗的限 制，並且因為它的靈活性，可擴展到支持多種電源電壓設計。我們更提出了兩種方法去加速ILP的運算，從實驗結果可以看到我們的方法能有效的降低ILP運算 時間。此外，我們的方法也有著很大的彈性空間，藉由更改或新增ILP的限制方程式，可以很容易延伸至不同目標的電路分割問題。這種靈活性使得我們的ILP 方程式可以很容易的解決一般的三維積體電路分割問題。

As technology advances, 3D IC has gradually become a trend, because it is a novel technology, it requires new EDA technology, and partitioning is one of important items. This paper focus on partitioning from the architectural level, in order to maximize its benefit. First, we use the logical operators to solve the problem of 3D IC partitioning, and converted into integer linear programs (ILPs). Our ILP formulation can reduce the number of TSV and power, and because of its flexibility, it can be expanded to support multiple supply voltage designs. We propose two methods to speed up the ILP computation, Experimental results show that our method can effectively reduce the ILP computation time. In addition, our method also has great flexibility in space, by restrictions on changes or new ILP formula can easily be extended to different target partitioning problem. This flexibility makes the ILP formula we can easily solve the general 3D IC partitioning problem.