一種應用於全差動連續近似式類比數位轉換器之混合訊號式校正方法

Abstract

SAR ADC的解析度主要受限於製程製作出的電容比例是否準確。本論文提出一種適用於全差動SAR ADC的混和訊號式校正方式。對於一個由已知比例關係之方式所構成的待校電容陣列，我們可以使用此演算法去找出該陣列中各個電容因製程變異而產生的誤差量，並將之數位化後儲存。然後，在SAR ADC進行轉換的同時補償每次DAC轉換所產生的誤差，如此便可提升該SAR ADC的解析度。 本論文提出之校正方式，不論電容因製程的非理想性導致其值比標準值高或低，都有辦法做到誤差計算與補償，並且使比較器的設計難度降低，有效的提升了SA ADC的有效位元數。 模擬結果顯示，靜態參數的表現上校正前INL=-11/+11LSB，校正後INL=-0.9/+0.9LSB，動態參數的表現上，校正前SNDR=51.7dB，ENOB=8.3bits，校正後peak SNDR=71.6dB，ENOB=11.6bits，可大幅改善因電容不匹配所造成的非線性。實作晶片量測結果顯示，未啟動校正機制時，當取樣頻率為10M S/s時，peak SNDR=53.3dB，ENOB=8.6bits，而校正後之peak SNDR=53.3dB，ENOB=8.6bits。雖然電路實現的量測結果顯示此校正法有未臻完美之處，但若我們能校正segmented架構中main DAC與sub DAC間的匹配度，將會使此演算法的可應用範圍大大提升。

It is the mismatched capacitors due to process variation that limit the resolution of a conventional capacitive SAR ADC. To address this issue, this thesis proposes a mixed-signal calibration scheme for the fully differential SAR ADC. The proposed calibration scheme first estimates the ratio errors of the capacitors under calibration in the binary weighted capacitor array. Then, the errors will be digitized and stored. When the SAR ADC operates in the normal conversion, the calibration scheme will compensate the errors caused by the DAC in an analog way. The calibration scheme proposed in this thesis is able to calibrate the ratio errors of the capacitors, no matter the ratio error is positive or negative. With the proposed calibration scheme, the effective number of bits of the SAR ADC can be enhanced. Simulation results show that the INL values are improved from -11~+11 LSB to -0.9~+0.9 LSB after calibration, and the SNDR and ENOB values are enhanced from 51.7dB and 8.3bits to 71.6dB and 11.6bits after calibration. The results show that the ADC’s performance can be significantly improved with the proposed calibration scheme. We implemented a 12-bit 1.8V SAR ADC with the proposed calibration scheme in TSMC 0.18µm 1P6M CMOS process. Measurement results show that the SAR ADC achieves SNDR of 53.3dB and ENOB of 8.6 bits at 10 MS/s before calibration. The ADC consumes 5.94mW at 1.8-V. The measurement results show this calibration method can be improved. The main issue is the mismatch between the main DAC and the sub DAC in the segmented structure. It is our future work to address this issue.