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dc.contributor.author王星雅en_US
dc.contributor.authorWang, Hsing-Yaen_US
dc.contributor.author蔡尚澕en_US
dc.contributor.authorTsai, Shang-Hoen_US
dc.date.accessioned2014-12-12T01:38:05Z-
dc.date.available2014-12-12T01:38:05Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079712595en_US
dc.identifier.urihttp://hdl.handle.net/11536/44488-
dc.description.abstract在這篇論文,我們介紹一個可以應用於 LTE之單載波分頻多工系統中的可變長度快速傅立葉轉換器。這個2048/1536/1024/512/256/128-point可變長度快速傅立葉轉換是以 、 及 快速傅立葉轉換演算法,並且利用混和radix演算法去執行。為了在單載波分頻多工系統中利用單一個快速傅立葉轉換處理器同時處理傅立葉和反傅立葉運算,我們仔細地設計時間規畫。因此可以減少面積。為了能更完美地設計時間規劃,我們提出了每一級重新設定的控制和輸出重新排列時的早讀。我們利用Xilinx FPGA Vertex5-XC5VLX110T-FF1136去模擬操作在100M赫茲的快速傅立葉轉換處理器。zh_TW
dc.description.abstractIn this thesis, we present a variable FFT that can support multiple FFT/IFFT size for LTE SC-FDMA systems. The 2048/1024/512/128-point variable FFT is based on radix-2, radix-3 and FFT algorithm, and we use mixed-radix algorithm to perform them. To handle both FFT and IFFT operations required in the SC-FDMA systems using only one FFT/IFFT processor, we carefully schedule the timing plan. As a result, the required area can be reduced. For the architecture, we propose a ripple-like ON/OFF stage control and an early access of reordering to implement our proposed timing plan. The proposed variable FFT processor is implemented using Xilinx FPGA Vertex5-XC5VLX110T-FF1136 at 100MHz operation frequency.en_US
dc.language.isoen_USen_US
dc.subject單載波分頻多工系統zh_TW
dc.subject快速傅立葉轉換處理器zh_TW
dc.subjectLTEen_US
dc.subjectSC-FDMAen_US
dc.title一種用於上行LTE之單載波分頻多工系統的可變長度快速傅立葉轉換處理器zh_TW
dc.titleA Variable FFT /IFFT Processor for SC-FDMA Systems over Uplink LTE Applicationsen_US
dc.typeThesisen_US
dc.contributor.department電控工程研究所zh_TW
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