應用於無線傳輸系統之發射與接收積體電路設計

Abstract

本論文描述應用於無線傳輸系統之發射與接收器之積體電路設計，在發射機的設計上是一個具有高線性度以及高單邊帶抑制的直接降頻式前端發射機。此發射機包含本地振盪輸入緩衝級、除二電路、正交調變混頻器、三級的射頻電壓控制放大器、功率放大器驅動級以及直流偏移校正電路等等，其中在前端本地振盪輸入緩衝級利用級間諧振網路使得電路可以達到寬頻的運作，另外在功率放大器驅動級的輸出匹配採用諧振匹配方式來達到寬頻帶的發射輸出，此發射機亦包含了直流偏移校正電路和正交訊號相位補償以達到更高的效能表現。量測結果顯示，在單邊帶與載波的抑制效果分別可以達到55.2 dBc和56.3 dBc，而發射機的動態增益範圍在解析度是1 dB的情況下具有53 dB，且最大的相對增益誤差低於0.4 dB。利用OFDMA 64QAM-3/4調變訊號做測試，此發射機在發射+0.77 dBm的輸出功率時仍然具有-34.7 dB的誤差向量幅度，而量測的星座圖從輸出功率-2.3至-36.2 dBm時可低於1.5%。 在接收機電路設計方面是一個直接降頻和具有雜訊抑制的接收機前端電路。此接收機包含了低雜訊放大器、正交降頻混頻器、除二電路以及相對應之緩衝器和校正電路。其中低雜訊放大器與正交降頻混頻器是採取共電流的方式實現，並利用雙重交互耦合電容方式來進一步降低雜訊、提高增益以及減少電流損耗。量測結果顯示，雜訊指數在操作頻帶內介於4至4.55 dB的範圍而輸入返回損耗則小於-9 dB。增益方面有21 dB的轉換電壓增益和0.3 dB以內的增益平坦度。可變增益具有四個模式可從21 dB切換至5 dB。 此外在前端射頻接收電路的輸出端需要一個類比式基頻低通濾波器來增強訊號以及濾除頻帶外之不必要的干擾訊號，因此在類比基頻濾波器的設計上整體架構利用Chebyshev方式實現七階主動式電阻電容的類比基頻濾波器，並在後面加上三級可程式化之以運算放大器為基底的增益級。此濾波器可達到在1dB解析度下有59dB的增益控制範圍，且可調式的頻寬可從2 MHz到10MHz。 在前端接收電路的設計上，除了前述介紹之接收系統架構外，本論文亦實現了一個利用順向偏壓於基板本體和雙重耦合電流方式以達到低功率的低雜訊放大器。在量測結果顯示此放大器只消耗了2.16毫瓦，且供應電壓只有0.9伏，雜訊指數在最高功率增益的情況下可以低於3.38dB。

This dissertation presents the design of transceiver integrated circuits for wireless transmission systems. A direct conversion front-end transmitter with the properties of high linearity and high single sideband rejection ratio is proposed. The transmitter is composed of a LO input buffer followed by a divide-by-2 circuit, an I/Q modulator, a three-stage RF variable gain control (VGA), a power amplifier (PA) driver, and dc offset and sideband calibration circuits. The LO input buffer employs an inter-stage resonant network to perform wideband operation. Furthermore, the shunt resonantor is utilized in the output matching of the PA driver to obtain broadband output. The transmitter also comprises the dc offset and I/Q phase calibration circuits to achieve higher performance. The measured sideband and carrier suppression signals are 55.2 dBc and 56.3 dBc, respectively. The dynamic gain range of the transmitter is 53 dB in 1 dB resolution with a maximum relative gain error lower than 0.4 dB. The transmitter delivers +0.77 dBm output power with error vector magnitude (EVM) of -34.7 dB for the orthogonal frequency division multiple access (OFDMA) 64QAM-3/4 modulated signals. The measured constellation can be minimized to be < 1.5 % with output power from -2.3 to -36.2 dBm. For the receiver design, a direct conversion front-end receiver with noise reduction is proposed. The receiver comprises a low noise amplifier (LNA), an I/Q mixer and a divide-by-2 circuit with its buffers. The merged LNA-I/Q-Mixer is implemented in the concurrent design. A dual cross coupling capacitor network is also employed to further reduce noise figure, increase overall voltage gain, and decrease the current consumption. The measured noise figure ranges from 4 ~ 4.55 dB and input return loss is less than -9 dB at the desired band. The receiver achieves a 21 dB conversion gain with less than 0.3 dB gain flatness at the highest gain mode and exhibits four gain states from 21 to 5 dB. Moreover, in the output stage of the RF front-end receiving circuit, an analog low pass filter is necessary to boost in-band signals and reject unwanted out-band signals. Consequently, an analog 7-order Chebyshev baseband filter with 3-stage programmable gain control amplifier (PGA) is designed. The filter achieves 59 dB gain control with 1 dB resolution and the pass-band ripple is smaller than 0.5 dB. The variable bandwidth is from 2 to 10MHz, respectively. In the front-end receiving circuit, in addition to the previous topology, a low power LNA with forward body bias and dual cross is also presented in the dissertation. The core circuit only consumes 2.16 mW at the supply voltage 0.9 V. The measured noise figure is lower than 3.38 dB at the highest power gain.