具有高介電質閘極氧化層(二氧化鉿、氧化鑭)之三五族金氧半電容其電性提升之研究

Abstract

傳統的互補式金氧半場效電晶體將在此世代遇到發展的瓶頸，而為了延續發展以及提升元件的特性，結合高介電質材料與高載子遷移率三五族半導體的研究逐漸受到重視。由於擁有極佳的載子傳輸特性，三五族復合物半導體將是未來通道材料的首選，因其擁有高速及低操作偏壓的元件特性。而採用高介電質材料作為閘極介電層是為了要抑制因元件尺寸的微縮所造成嚴重的閘極漏電流。然而高介電質材料與三五族半導體之間的界面問題始終阻礙著三五族金氧半元件的發展。本論文主要是利用分子束磊晶機台來沉積高品質的高介電質材料(二氧化鉿、氧化鑭)於三五族複合物半導體基板上來製備金氧半電容，並尋求各種可行的方法來改善介面品質以提升元件特性。 由本實驗結果顯示，二氧化鉿與砷化銦之間的界面品質可藉由較高的退火溫度來改善，而元件特性也隨之提升。然而，當退火溫度高於500℃，銦原子會由基板擴散至二氧化鉿，在界面有大量的氧化銦產生，導致元件特性因此變差。同時也研究出具有高介電常數的氧化鑭與砷化銦鎵之間有劇烈的交互作用，因此無法獲得低缺陷的界面品質。藉由嵌入一層熱穩定的二氧化鉿形成層狀堆疊的閘極介電層可改善介面問題並提升元件的電容值，並在具有高銦含量的電容上顯示出明顯的載子反轉行為。最後，兩階段退火處理對於元件特性的影響也同時被研究，而結果顯示出兩階段退火更能顯著的降低表面缺陷密度且獲得品質較佳的閘極氧化層。

To extent the limit of traditional Si-based MOS-devices, high-mobility channel materials and high dielectric constant (high-κ) materials as gate dielectrics for CMOS have been extensively studied. InXGa1-XAs-channel has attracted much attention due to the much superior carrier mobility, especially electron mobility, than Si. Among many high-κ dielectric materials, HfO2 is more attractive than other high-κ materials in terms of its high dielectric constant (κ~20-25), large energy band gap (~6eV), and thermally stable on III-V materials. Furthermore, rare-earth oxides (REOs) possess high dielectric constant and are expected to be used as gate dielectric materials for post-HfO2 oxide era. However, the lack of high quality oxide/III-V semiconductor interface, especially REOs, is the main obstacle for the development for III-V MOSFETs. In this thesis, molecular beam epitaxy (MBE) was used to deposit high quality high-κ thin films on III-V MOS-capacitors. Post deposition annealing (PDA) was performed after the gate oxide deposition and optimized to improve the device performance. The MOS-capacitor after the 500 oC PDA annealing demonstrated the lowest interface trap density (Dit) value due to the reduction of native oxide (As2O3). However, as the annealing temperature approached 550 oC, a large number of indium (In) atoms diffused into the HfO2 layer with the increase of InOX and In2O3 formation so that the device performance was degraded. Inserting a thin interlayer (IL) between REO and III-V channel can prevent their inter-reaction and enhance the capacitance value. The capacitance enhance in the accumulation region due to the addition of La2O3 as compared to pure HfO2/ InXGa1-XAs MOS-capacitor from 0.73 (μF/cm2) to 1.26 (μF/cm2) for n-InAs capacitor, and from 0.5 (μF/cm2) to 1.05 (μF/cm2) for p-In0.7Ga0.3As capacitor. The two-steps annealing is a useful thermal treatment to obtain a low Dit and a small hysteresis value. The C-V characteristics would be improved after the second annealing with the small frequency dispersion. The experiment results also showed that a large temperature difference between the first step and the second step would cause the more serious hysteresis effect due to a large lattice mismatch between the two oxide layers.