EFFICIENT BIT-LEVEL SYSTOLIC ARRAY IMPLEMENTATION OF FIR AND IIR DIGITAL-FILTERS

標題:	EFFICIENT BIT-LEVEL SYSTOLIC ARRAY IMPLEMENTATION OF FIR AND IIR DIGITAL-FILTERS
作者:	WANG, CL WEI, CH CHEN, SH 電控工程研究所電信工程研究所 Institute of Electrical and Control Engineering Institute of Communications Engineering
公開日期:	1-Apr-1988
URI:	http://dx.doi.org/10.1109/49.1916 http://hdl.handle.net/11536/4539
ISSN:	0733-8716
DOI:	10.1109/49.1916
期刊:	IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS
Volume:	6
Issue:	3
起始頁:	484
結束頁:	493
Appears in Collections:	Articles

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