考慮單元切換時間之基於叢集法以有效配置去耦合電容使供電干擾最小化

Abstract

隨著製程不斷的進步以及供應電壓源的縮小，供電干擾在現代的晶片設計對於電路的效能有很大的影響，嚴重的供電干擾甚至會造成整顆晶片無法正常運作。去耦合電容為目前最普遍使用的方法以改進供電干擾。由於在布局之後插入去耦合電容有可能會破壞原本的佈局對於繞線長度和延遲時間的最佳化，所以我們在布局之前提出一個基於預測機制的方法來去配置去耦合電容，這個預測機制的方法包含一個考慮單元切換時間之叢集法和一個去耦合電容之預測策畫。有些地方在布局之後無法完全去解決還存在著嚴重的供電干擾，因此在去耦合電容的量是有限的情況下我們提出一個去耦合電容之重新分配法來進一步減少供電干擾。最後，實驗數據結果說明我們的整套設計流程跟先前的論文[2]比較上，在降低供電干擾可以有不錯的表現而且繞線長度和執行時間也來得比較短。

Power noise extremely impact the circuit performance in modern design as voltage sources and the chip size are continuously scaling. Serious power noise may cause function faults in a circuit. Decoupling Capacitor (decap) allocation is widely employed to improve power noises. Due to the decap allocation after placement may damage the former objectives as timing and wirelength optimization, this study proposes a prediction-based mechanism composed of a transition-aware clustering and a decap prediction scheme to allocate decaps before placement. If the hotspot regions with severe power noise are unable to be completely solved after placement, a decap reallocation method is used to further reduce power noise by a decap budget constraint. Finally, experimental results show that our design flow achieves better quality in suppressing power noise, lower wirelength and runtime than the previous work [2].