標題: 提升最大工作週期之電容電壓偵測與控制於使用自舉電容的降壓電源轉換器
Maximum Duty Cycle Enhancement of Capacitor Voltage Detection and Control in Buck Converter with Bootstrapped Capacitor
作者: 郭築衛
Kuo, Chu-Wei
陳科宏
Chen, Ke-Horng
電機學院電機與控制學程
關鍵字: 最大工作週期;電容電壓偵測;自舉電容;Maximum Duty Cycle;Capacitor Voltage Detection;Bootstrapped Capacitor
公開日期: 2011
摘要: 此論文提出一電容電壓偵測方法和充電時間控制於使用自舉電容之直流降壓電源轉換器。由於佈局面積小使得成本降低的優點與等效導通電阻小的特性,N通道金氧半場效體被廣泛的使用於直流降壓電源轉換器之上橋驅動元件,但是需要自舉電容提供足夠的閘極電壓使場效體工作正常,並降低等效導通電阻。然而,自舉電容提供閘極電壓時會消耗電荷使電壓降低,需要時常充電,因此,最大工作週期設定以利用上橋驅動元件截止時間來對自舉電容充電是常用的方式。但最大工作週期雖使得系統穩定卻讓輸出電壓有最高限制,這樣縮小了切換式電源轉換器的使用範圍。因此,具電容電壓偵測能力和充電時間控制的電路在此被提出以提高輸出電壓的範圍,並提高系統在輸出電壓接近輸入電壓時的效率。同時,此技術的使用只需增加小於11 μA的工作電流,也不會提高電路的複雜度。使得在輸出負載2安培的狀況下輸出電壓可達到輸入電壓的98.5%,輸出漣波電壓小於輸出電壓之2%,也因工作頻率降低五十倍以上,減少切換損耗使工作效率提昇,而自舉電容電壓偵測之誤差比率小於2%。模擬結果說明了在輸出電壓接近輸入電壓時的使用仍可以保持系統的穩定性。在如此的條件下,相較於傳統的最大工作週期控制法,系統可操作的輸出電壓限制從90%被大大提昇至98.5%並提供高效率和低輸出漣波電壓表現。
Capacitor voltage detection with adequate charge time control is proposed in DC-DC buck converter with the bootstrapped capacitor in this thesis. N-channel MOSFET is widely used as the high-side power switch of DC-DC buck converter due to small silicon area and low equivalent turn-on resistance. However, the N-channel MOSFET needs bootstrapped capacitor to provide enough gate-source voltage for lowering equivalent turn-on resistance and thus enhancing power conversion efficiency. The bootstrapped capacitor needs to be charged frequently because the voltage across it decreases when it drives the gate driver of the N-channel MOSFET. Thus maximum duty cycle setting that uses the off time of high-side power switch during every period to charge bootstrap capacitor is popularly used in conventional methods. Thus, it can lead to stable system but it limits the maximum applicable output voltage and reduces the flexibility of DC-DC buck converter. Therefore, the ability of capacitor voltage detection and charge time control can increase the achievable output voltage level. In the meanwhile, the extra power dissipation is smaller than 11 μA with a low complexity in the circuit design. The output voltage can be close to 98.5 % of input voltage when the load current is 2 A with the ripple voltage smaller than 2 % of the output voltage. Furthermore, the reduced operation frequency near 1/50 of original oscillator frequency can effectively improve the power conversion efficiency due to the reduction of the switching loss. The error percentage of capacitor voltage detection is lower than 2 % compared with the reference voltage. The simulation results that the system is stable when the output voltage approaches the input voltage, that is, the duty is close to 100%. Compared with the conventional maximum duty cycle control techniques, the limit of the applicable output voltage is much improved to 98.5 % with high efficiency and low output voltage ripple.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079767519
http://hdl.handle.net/11536/46305
顯示於類別:畢業論文