完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 鄭世東 | en_US |
dc.contributor.author | Cheng, Shih-Tung | en_US |
dc.contributor.author | 洪崇智 | en_US |
dc.contributor.author | Hung, Chung-Chih | en_US |
dc.date.accessioned | 2014-12-12T01:45:49Z | - |
dc.date.available | 2014-12-12T01:45:49Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT079792501 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/46599 | - |
dc.description.abstract | 隨著製程的演進,電路系統的工作電壓也越來越低,對數位電路來說,當工作電壓越低,能夠在相同的電路功能下有更低的消耗功率,這在手持式電子商品已成為主流的現在,降低工作電壓來節省功率消耗無疑是未來的趨勢。但對於類比電路而言,較低的工作電壓,帶來的不單單是效能的降低,很多原本實用的電路架構,在低工作電壓下根本無法正常作動,因此如何創新電路設計,來使類比電路在低電壓環境下仍能有著相同甚至更好的效能,就成為類比電路設計一個熱門的課題。 本論文提出兩種改善三極區轉導放大器線性度的方法。並分別達成了高轉導值調整範圍、低工作電壓以及高線性訊號輸入範圍,並且兩者的消耗功率都極低。第一種是將輸入對電晶體偏壓在三極區,並加入一組弱反轉區輸入對,以抵消第三階諧波失真,其工作電壓為1.2V並消耗功率0.226mW。當輸入信號頻率為0.4Vpp時,可達成第三階諧波失真-71.3dB。此轉導放大器是以台積電0.18μm CMOS 1P6M 製程實現,使用面積為 。 第二種轉導放大器也是將輸入對電晶體偏壓在三極區,並加入了高效能的遷移率補償機制,成功壓低了22.4dB的第三階諧波失真。其工作電壓為1.8V並消耗功率427mW。當輸入信號頻率為1.2Vpp時,可達成第三階諧波失真-79dB。此轉導放大器是以台積電0.18μm CMOS 1P6M 製程實現,使用面積為 。 | zh_TW |
dc.description.abstract | With the evolution of the fabrication technology, the supply voltage of the electric circuit systems has become lower and lower. Since portable electronic devices are getting very popular, it is the trend to lower power supply voltage in order to decrease power consumption. For digital circuits, when the power supply reduces, the power consumption would be lower while circuit performance stays the same. However, for analog circuits, the low voltage supply might not only bring the downgrade of circuit performance, but also cause failure of some basic circuit structures. It has attracted lots of attentions to design analog circuits to work under low voltage conditions. Two circuits have been proposed to improve the linearity of the transconductors working in the triode region. High transconductance tuning range, low voltage supply, and high linearity are all achieved in the design. The first circuit is designed by biasing input transistor pair in the triode region, in parallel with another input pair working in the weak inversion region, to cancel out the third order harmonic distortion. The power supply voltage is 1.2V and the circuit consumes 0.226mW. The third order harmonic distortion of -71.3dB is achieved with the input signal of 0.4Vpp. The transconductor fabricated by TSMC 0.18um CMOS 1P6M technology occupies the area of . The second transconductor also biases the input transistor pair in the triode region. In addition, high performance mobility compensation mechanism has been implemented. It has successfully suppressed the third order harmonic distortion by 22.4dB. The supply voltage is 1.8V and the circuit consumes 427uW. The third order harmonic distortion of -79dB is achieved with the input signal of 1.2Vpp. The transconductor fabricated by TSMC 0.18um CMOS technology occupies the area of . | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 轉導放大器 | zh_TW |
dc.subject | 高線性度 | zh_TW |
dc.subject | transconductor | en_US |
dc.subject | high linearity | en_US |
dc.title | 使用三極區偽差動輸入對之高線性度互補金氧半轉導放大器 | zh_TW |
dc.title | High linearity CMOS transconductors with triode-region pseudo-differential input pair | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電機學院通訊與網路科技產業專班 | zh_TW |
顯示於類別: | 畢業論文 |