具有混合邏輯與電阻式切換特性之複晶矽薄膜

Abstract

在本論文中，透過使用二氧化鉿(HfO2)做閘極介電層與金屬鎳閘極的結構， 我們成功將電阻式切換特性與傳統電晶體結構結合，其中二氧化鉿扮演電阻式記 憶體中的切換層，而金屬鎳閘極則扮演了電阻式記憶體中上電極的功用。 在一開始先探討利用電晶體單一端點做電阻式切換的特性，我們首先透過閘 極或汲極作為電阻式切換的電壓提供端。透過實驗我們發現，利用閘極做電壓提 供端的操作模式在電阻切換後有顯著的臨界電壓偏移情形，但是在利用汲極作為 切換電壓提供端且源極接地時的操作卻發現不會有這樣顯著的偏移情況發生。 在第二部分透過電壓應力的實驗，我們探討在不同端點不同偏壓下所發生的 電荷捕捉情況，也由此證明在電阻式切換的操作過程中的確會發生電荷捕捉情況 進而造成電晶體臨界電壓的改變。 最後我們透過適當的操作方式，成功實現不會造成顯著臨界電壓偏移且有穩 定電阻式切換特性的雙端操作(two-bit operation)，到此我們可以說：第一個利用 電阻式切換機制的雙位元電晶體(two-bit-per cell)被成功展現出來。

A hybrid device combined a resistive switching (RS) memory and a logic transistor is proposed in this thesis. The hafnium oxide (HfO2) is not only the high-κ gate dielectric of the transistor but also the resistive switching layer of the RRAM, and the nickel metal gate also acts like a top electrode in a traditional MIM or MIS which is the most common structure in the previous RRAM paper . We first demonstrated a one-bit RS operation by applying a swept voltage on either the gate or drain to trigger the RS. A large amount of VT shift after the RS operation was found when we applied voltage on the gate. On the other hand, the VT shift is negligible when we swept the drain voltage with source grounded during the set/reset process. With the help of the constant voltage stress experiment, we realized that the reason caused the considerable VT shift after resistive switching operation was the charge trapping and wearout attributed to the high voltage applied during the set/reset process, which might induce F-N tunneling. iii Finally, we realized a two-bit-per cell operation mode in our structure with almost negligible VT shift after RS for the first time, which indicated that a new type of high-density memory using the resistive switching mechanism in a traditional transistor structure is possible.