快速提供佈局原型之奈米級類比電路設計遷徙

Abstract

傳統的製程遷徙技術往往只產生單一的遷徙後佈局，此與原始佈局有著完全相同的拓樸關係。然而，隨著遷徙至不同的製程或設計規格，元件佈局的尺寸或面積必定有所改變，若將設計者在原始佈局上的考量直接套用在遷徙後佈局，會使得遷徙後佈局不一定能達到其所預想達成的效能規格。為了能給予設計者在製程遷徙上更多的彈性，本篇論文提出一個新的演算法，能夠快速提供多種擁有不同寬高比的擺置結果。首先，從原始佈局中萃取出各種擺置限制，包含元件佈局之間的拓樸、匹配以及對稱的關係。這些擺置限制會被階層式地儲存於一個拓樸切割樹中。基於此樹，擺置演算法由下而上將多種的子節點擺放結果記錄在每一個子樹。當進行到根節點，則可得到所有可能的不同寬高比之擺置結果。實驗數據顯示，本篇論文可以快速地提供合理甚至是更好效能的佈局結果。

Traditional migration technology often generates a single layout that has exactly the same topology with the original one. However, as a circuit is retargeted to a new technology or new specification, the new result with exactly the same topology may not be the desired placement in the migrated technology because of the layout dimension or the layout area. In order to provide sufficient flexibility for designers, a new migration algorithm proposed in this thesis is able to quickly provide multiple results while keeping similar circuit performance. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Based on this tree, placement is performed from the bottom tree nodes to the root tree node to record multiple placements for the subtree. As a result, all possible placements under the constraints will be fully explored. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.